1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <i2c.h> 11 12 #include <asm/fsl_ddr_sdram.h> 13 14 static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) 15 { 16 i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); 17 } 18 19 unsigned int fsl_ddr_get_mem_data_rate(void) 20 { 21 return get_ddr_freq(0); 22 } 23 24 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, 25 unsigned int ctrl_num) 26 { 27 unsigned int i; 28 unsigned int i2c_address = 0; 29 30 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 31 if (ctrl_num == 0 && i == 0) { 32 i2c_address = SPD_EEPROM_ADDRESS1; 33 } 34 if (ctrl_num == 1 && i == 0) { 35 i2c_address = SPD_EEPROM_ADDRESS2; 36 } 37 get_spd(&(ctrl_dimms_spd[i]), i2c_address); 38 } 39 } 40 41 void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) 42 { 43 /* 44 * Factors to consider for clock adjust: 45 * - number of chips on bus 46 * - position of slot 47 * - DDR1 vs. DDR2? 48 * - ??? 49 * 50 * This needs to be determined on a board-by-board basis. 51 * 0110 3/4 cycle late 52 * 0111 7/8 cycle late 53 */ 54 popts->clk_adjust = 7; 55 56 /* 57 * Factors to consider for CPO: 58 * - frequency 59 * - ddr1 vs. ddr2 60 */ 61 popts->cpo_override = 10; 62 63 /* 64 * Factors to consider for write data delay: 65 * - number of DIMMs 66 * 67 * 1 = 1/4 clock delay 68 * 2 = 1/2 clock delay 69 * 3 = 3/4 clock delay 70 * 4 = 1 clock delay 71 * 5 = 5/4 clock delay 72 * 6 = 3/2 clock delay 73 */ 74 popts->write_data_delay = 5; 75 76 /* 77 * Factors to consider for half-strength driver enable: 78 * - number of DIMMs installed 79 */ 80 popts->half_strength_driver_enable = 0; 81 } 82