1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <i2c.h> 11 12 #include <asm/fsl_ddr_sdram.h> 13 #include <asm/fsl_ddr_dimm_params.h> 14 15 static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) 16 { 17 i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); 18 } 19 20 unsigned int fsl_ddr_get_mem_data_rate(void) 21 { 22 return get_ddr_freq(0); 23 } 24 25 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, 26 unsigned int ctrl_num) 27 { 28 unsigned int i; 29 unsigned int i2c_address = 0; 30 31 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 32 if (ctrl_num == 0 && i == 0) { 33 i2c_address = SPD_EEPROM_ADDRESS1; 34 } 35 if (ctrl_num == 1 && i == 0) { 36 i2c_address = SPD_EEPROM_ADDRESS2; 37 } 38 get_spd(&(ctrl_dimms_spd[i]), i2c_address); 39 } 40 } 41 42 typedef struct { 43 u32 datarate_mhz_low; 44 u32 datarate_mhz_high; 45 u32 n_ranks; 46 u32 clk_adjust; 47 u32 cpo; 48 u32 write_data_delay; 49 u32 force_2T; 50 } board_specific_parameters_t; 51 52 /* ranges for parameters: 53 * wr_data_delay = 0-6 54 * clk adjust = 0-8 55 * cpo 2-0x1E (30) 56 */ 57 58 59 /* XXX: these values need to be checked for all interleaving modes. */ 60 /* XXX: No reliable dual-rank 800 MHz setting has been found. It may 61 * seem reliable, but errors will appear when memory intensive 62 * program is run. */ 63 /* XXX: Single rank at 800 MHz is OK. */ 64 const board_specific_parameters_t board_specific_parameters[][20] = { 65 { 66 /* memory controller 0 */ 67 /* lo| hi| num| clk| cpo|wrdata|2T */ 68 /* mhz| mhz|ranks|adjst| | delay| */ 69 { 0, 333, 2, 6, 7, 3, 0}, 70 {334, 400, 2, 6, 9, 3, 0}, 71 {401, 549, 2, 6, 11, 3, 0}, 72 {550, 680, 2, 1, 10, 5, 0}, 73 {681, 850, 2, 1, 12, 5, 1}, 74 { 0, 333, 1, 6, 7, 3, 0}, 75 {334, 400, 1, 6, 9, 3, 0}, 76 {401, 549, 1, 6, 11, 3, 0}, 77 {550, 680, 1, 1, 10, 5, 0}, 78 {681, 850, 1, 1, 12, 5, 0} 79 }, 80 81 { 82 /* memory controller 1 */ 83 /* lo| hi| num| clk| cpo|wrdata|2T */ 84 /* mhz| mhz|ranks|adjst| | delay| */ 85 { 0, 333, 2, 6, 7, 3, 0}, 86 {334, 400, 2, 6, 9, 3, 0}, 87 {401, 549, 2, 6, 11, 3, 0}, 88 {550, 680, 2, 1, 11, 6, 0}, 89 {681, 850, 2, 1, 13, 6, 1}, 90 { 0, 333, 1, 6, 7, 3, 0}, 91 {334, 400, 1, 6, 9, 3, 0}, 92 {401, 549, 1, 6, 11, 3, 0}, 93 {550, 680, 1, 1, 11, 6, 0}, 94 {681, 850, 1, 1, 13, 6, 0} 95 } 96 }; 97 98 void fsl_ddr_board_options(memctl_options_t *popts, 99 dimm_params_t *pdimm, 100 unsigned int ctrl_num) 101 { 102 const board_specific_parameters_t *pbsp = 103 &(board_specific_parameters[ctrl_num][0]); 104 u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / 105 sizeof(board_specific_parameters[0][0]); 106 u32 i; 107 ulong ddr_freq; 108 109 /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in 110 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If 111 * there are two dimms in the controller, set odt_rd_cfg to 3 and 112 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. 113 */ 114 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 115 if (i&1) { /* odd CS */ 116 popts->cs_local_opts[i].odt_rd_cfg = 0; 117 popts->cs_local_opts[i].odt_wr_cfg = 0; 118 } else { /* even CS */ 119 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { 120 popts->cs_local_opts[i].odt_rd_cfg = 0; 121 popts->cs_local_opts[i].odt_wr_cfg = 4; 122 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { 123 popts->cs_local_opts[i].odt_rd_cfg = 3; 124 popts->cs_local_opts[i].odt_wr_cfg = 3; 125 } 126 } 127 } 128 129 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 130 * freqency and n_banks specified in board_specific_parameters table. 131 */ 132 ddr_freq = get_ddr_freq(0) / 1000000; 133 for (i = 0; i < num_params; i++) { 134 if (ddr_freq >= pbsp->datarate_mhz_low && 135 ddr_freq <= pbsp->datarate_mhz_high && 136 pdimm->n_ranks == pbsp->n_ranks) { 137 popts->clk_adjust = pbsp->clk_adjust; 138 popts->cpo_override = pbsp->cpo; 139 popts->write_data_delay = pbsp->write_data_delay; 140 popts->twoT_en = pbsp->force_2T; 141 } 142 pbsp++; 143 } 144 145 /* 146 * Factors to consider for half-strength driver enable: 147 * - number of DIMMs installed 148 */ 149 popts->half_strength_driver_enable = 0; 150 } 151