1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0
2129ba616SKumar Gala /*
3129ba616SKumar Gala * Copyright 2008 Freescale Semiconductor, Inc.
4129ba616SKumar Gala */
5129ba616SKumar Gala
6129ba616SKumar Gala #include <common.h>
7129ba616SKumar Gala
85614e71bSYork Sun #include <fsl_ddr_sdram.h>
95614e71bSYork Sun #include <fsl_ddr_dimm_params.h>
10129ba616SKumar Gala
11712cf7abSYork Sun struct board_specific_parameters {
124ca06607SHaiying Wang u32 n_ranks;
13712cf7abSYork Sun u32 datarate_mhz_high;
144ca06607SHaiying Wang u32 clk_adjust;
154ca06607SHaiying Wang u32 cpo;
164ca06607SHaiying Wang u32 write_data_delay;
170dd38a35SPriyanka Jain u32 force_2t;
18712cf7abSYork Sun };
194ca06607SHaiying Wang
20634bc554SYork Sun /*
21712cf7abSYork Sun * This table contains all valid speeds we want to override with board
22712cf7abSYork Sun * specific parameters. datarate_mhz_high values need to be in ascending order
23712cf7abSYork Sun * for each n_ranks group.
24634bc554SYork Sun *
25634bc554SYork Sun * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
26634bc554SYork Sun * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
27634bc554SYork Sun * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
28634bc554SYork Sun * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
29634bc554SYork Sun * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
30712cf7abSYork Sun *
31712cf7abSYork Sun * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
324ca06607SHaiying Wang */
33712cf7abSYork Sun static const struct board_specific_parameters udimm0[] = {
34634bc554SYork Sun /*
35634bc554SYork Sun * memory controller 0
36712cf7abSYork Sun * num| hi| clk| cpo|wrdata|2T
37712cf7abSYork Sun * ranks| mhz|adjst| | delay|
38634bc554SYork Sun */
39712cf7abSYork Sun {2, 333, 8, 7, 5, 0},
40712cf7abSYork Sun {2, 400, 8, 9, 5, 0},
41712cf7abSYork Sun {2, 549, 8, 11, 5, 0},
42712cf7abSYork Sun {2, 680, 8, 10, 5, 0},
43712cf7abSYork Sun {2, 850, 8, 12, 5, 1},
44712cf7abSYork Sun {1, 333, 6, 7, 3, 0},
45712cf7abSYork Sun {1, 400, 6, 9, 3, 0},
46712cf7abSYork Sun {1, 549, 6, 11, 3, 0},
47712cf7abSYork Sun {1, 680, 1, 10, 5, 0},
48712cf7abSYork Sun {1, 850, 1, 12, 5, 0},
49712cf7abSYork Sun {}
504ca06607SHaiying Wang };
514ca06607SHaiying Wang
52712cf7abSYork Sun static const struct board_specific_parameters udimm1[] = {
53634bc554SYork Sun /*
54634bc554SYork Sun * memory controller 1
55712cf7abSYork Sun * num| hi| clk| cpo|wrdata|2T
56712cf7abSYork Sun * ranks| mhz|adjst| | delay|
57634bc554SYork Sun */
58712cf7abSYork Sun {2, 333, 8, 7, 5, 0},
59712cf7abSYork Sun {2, 400, 8, 9, 5, 0},
60712cf7abSYork Sun {2, 549, 8, 11, 5, 0},
61712cf7abSYork Sun {2, 680, 8, 11, 5, 0},
62712cf7abSYork Sun {2, 850, 8, 13, 5, 1},
63712cf7abSYork Sun {1, 333, 6, 7, 3, 0},
64712cf7abSYork Sun {1, 400, 6, 9, 3, 0},
65712cf7abSYork Sun {1, 549, 6, 11, 3, 0},
66712cf7abSYork Sun {1, 680, 1, 11, 6, 0},
67712cf7abSYork Sun {1, 850, 1, 13, 6, 0},
68712cf7abSYork Sun {}
69712cf7abSYork Sun };
70712cf7abSYork Sun
71712cf7abSYork Sun static const struct board_specific_parameters *udimms[] = {
72712cf7abSYork Sun udimm0,
73712cf7abSYork Sun udimm1,
74712cf7abSYork Sun };
75712cf7abSYork Sun
76712cf7abSYork Sun static const struct board_specific_parameters rdimm0[] = {
77712cf7abSYork Sun /*
78712cf7abSYork Sun * memory controller 0
79712cf7abSYork Sun * num| hi| clk| cpo|wrdata|2T
80712cf7abSYork Sun * ranks| mhz|adjst| | delay|
81712cf7abSYork Sun */
82712cf7abSYork Sun {2, 333, 4, 7, 3, 0},
83712cf7abSYork Sun {2, 400, 4, 9, 3, 0},
84712cf7abSYork Sun {2, 549, 4, 11, 3, 0},
85712cf7abSYork Sun {2, 680, 4, 10, 3, 0},
86712cf7abSYork Sun {2, 850, 4, 12, 3, 1},
87712cf7abSYork Sun {}
88712cf7abSYork Sun };
89712cf7abSYork Sun
90712cf7abSYork Sun static const struct board_specific_parameters rdimm1[] = {
91712cf7abSYork Sun /*
92712cf7abSYork Sun * memory controller 1
93712cf7abSYork Sun * num| hi| clk| cpo|wrdata|2T
94712cf7abSYork Sun * ranks| mhz|adjst| | delay|
95712cf7abSYork Sun */
96712cf7abSYork Sun {2, 333, 4, 7, 3, 0},
97712cf7abSYork Sun {2, 400, 4, 9, 3, 0},
98712cf7abSYork Sun {2, 549, 4, 11, 3, 0},
99712cf7abSYork Sun {2, 680, 4, 11, 3, 0},
100712cf7abSYork Sun {2, 850, 4, 13, 3, 1},
101712cf7abSYork Sun {}
102712cf7abSYork Sun };
103712cf7abSYork Sun
104712cf7abSYork Sun static const struct board_specific_parameters *rdimms[] = {
105712cf7abSYork Sun rdimm0,
106712cf7abSYork Sun rdimm1,
107634bc554SYork Sun };
108634bc554SYork Sun
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)109dfb49108SHaiying Wang void fsl_ddr_board_options(memctl_options_t *popts,
110dfb49108SHaiying Wang dimm_params_t *pdimm,
111dfb49108SHaiying Wang unsigned int ctrl_num)
112129ba616SKumar Gala {
113712cf7abSYork Sun const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
1144ca06607SHaiying Wang ulong ddr_freq;
115634bc554SYork Sun
116712cf7abSYork Sun if (ctrl_num > 1) {
117712cf7abSYork Sun printf("Wrong parameter for controller number %d", ctrl_num);
118712cf7abSYork Sun return;
119712cf7abSYork Sun }
120634bc554SYork Sun if (!pdimm->n_ranks)
121634bc554SYork Sun return;
122634bc554SYork Sun
123712cf7abSYork Sun if (popts->registered_dimm_en)
124712cf7abSYork Sun pbsp = rdimms[ctrl_num];
125712cf7abSYork Sun else
126712cf7abSYork Sun pbsp = udimms[ctrl_num];
127129ba616SKumar Gala
1284ca06607SHaiying Wang /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
1294ca06607SHaiying Wang * freqency and n_banks specified in board_specific_parameters table.
130129ba616SKumar Gala */
1314ca06607SHaiying Wang ddr_freq = get_ddr_freq(0) / 1000000;
132712cf7abSYork Sun while (pbsp->datarate_mhz_high) {
133712cf7abSYork Sun if (pbsp->n_ranks == pdimm->n_ranks) {
134712cf7abSYork Sun if (ddr_freq <= pbsp->datarate_mhz_high) {
1354ca06607SHaiying Wang popts->clk_adjust = pbsp->clk_adjust;
1364ca06607SHaiying Wang popts->cpo_override = pbsp->cpo;
137712cf7abSYork Sun popts->write_data_delay =
138712cf7abSYork Sun pbsp->write_data_delay;
1390dd38a35SPriyanka Jain popts->twot_en = pbsp->force_2t;
140712cf7abSYork Sun goto found;
141712cf7abSYork Sun }
142712cf7abSYork Sun pbsp_highest = pbsp;
1434ca06607SHaiying Wang }
1444ca06607SHaiying Wang pbsp++;
1454ca06607SHaiying Wang }
146129ba616SKumar Gala
147712cf7abSYork Sun if (pbsp_highest) {
148712cf7abSYork Sun printf("Error: board specific timing not found "
149712cf7abSYork Sun "for data rate %lu MT/s!\n"
150712cf7abSYork Sun "Trying to use the highest speed (%u) parameters\n",
151712cf7abSYork Sun ddr_freq, pbsp_highest->datarate_mhz_high);
152712cf7abSYork Sun popts->clk_adjust = pbsp->clk_adjust;
153712cf7abSYork Sun popts->cpo_override = pbsp->cpo;
154712cf7abSYork Sun popts->write_data_delay = pbsp->write_data_delay;
1550dd38a35SPriyanka Jain popts->twot_en = pbsp->force_2t;
156712cf7abSYork Sun } else {
157712cf7abSYork Sun panic("DIMM is not supported by this board");
158939e5bf9SYork Sun }
159634bc554SYork Sun
160712cf7abSYork Sun found:
161129ba616SKumar Gala /*
162129ba616SKumar Gala * Factors to consider for half-strength driver enable:
163129ba616SKumar Gala * - number of DIMMs installed
164129ba616SKumar Gala */
165129ba616SKumar Gala popts->half_strength_driver_enable = 0;
166129ba616SKumar Gala }
167