1129ba616SKumar Gala /* 2129ba616SKumar Gala * Copyright 2008 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 4129ba616SKumar Gala * This program is free software; you can redistribute it and/or 5129ba616SKumar Gala * modify it under the terms of the GNU General Public License 6129ba616SKumar Gala * Version 2 as published by the Free Software Foundation. 7129ba616SKumar Gala */ 8129ba616SKumar Gala 9129ba616SKumar Gala #include <common.h> 10129ba616SKumar Gala #include <i2c.h> 11129ba616SKumar Gala 12129ba616SKumar Gala #include <asm/fsl_ddr_sdram.h> 13*dfb49108SHaiying Wang #include <asm/fsl_ddr_dimm_params.h> 14129ba616SKumar Gala 15129ba616SKumar Gala static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) 16129ba616SKumar Gala { 17129ba616SKumar Gala i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); 18129ba616SKumar Gala } 19129ba616SKumar Gala 20129ba616SKumar Gala unsigned int fsl_ddr_get_mem_data_rate(void) 21129ba616SKumar Gala { 22129ba616SKumar Gala return get_ddr_freq(0); 23129ba616SKumar Gala } 24129ba616SKumar Gala 25129ba616SKumar Gala void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, 26129ba616SKumar Gala unsigned int ctrl_num) 27129ba616SKumar Gala { 28129ba616SKumar Gala unsigned int i; 29129ba616SKumar Gala unsigned int i2c_address = 0; 30129ba616SKumar Gala 31129ba616SKumar Gala for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 32129ba616SKumar Gala if (ctrl_num == 0 && i == 0) { 33129ba616SKumar Gala i2c_address = SPD_EEPROM_ADDRESS1; 34129ba616SKumar Gala } 35129ba616SKumar Gala if (ctrl_num == 1 && i == 0) { 36129ba616SKumar Gala i2c_address = SPD_EEPROM_ADDRESS2; 37129ba616SKumar Gala } 38129ba616SKumar Gala get_spd(&(ctrl_dimms_spd[i]), i2c_address); 39129ba616SKumar Gala } 40129ba616SKumar Gala } 41129ba616SKumar Gala 42*dfb49108SHaiying Wang void fsl_ddr_board_options(memctl_options_t *popts, 43*dfb49108SHaiying Wang dimm_params_t *pdimm, 44*dfb49108SHaiying Wang unsigned int ctrl_num) 45129ba616SKumar Gala { 46129ba616SKumar Gala /* 47129ba616SKumar Gala * Factors to consider for clock adjust: 48129ba616SKumar Gala * - number of chips on bus 49129ba616SKumar Gala * - position of slot 50129ba616SKumar Gala * - DDR1 vs. DDR2? 51129ba616SKumar Gala * - ??? 52129ba616SKumar Gala * 53129ba616SKumar Gala * This needs to be determined on a board-by-board basis. 54129ba616SKumar Gala * 0110 3/4 cycle late 55129ba616SKumar Gala * 0111 7/8 cycle late 56129ba616SKumar Gala */ 57129ba616SKumar Gala popts->clk_adjust = 7; 58129ba616SKumar Gala 59129ba616SKumar Gala /* 60129ba616SKumar Gala * Factors to consider for CPO: 61129ba616SKumar Gala * - frequency 62129ba616SKumar Gala * - ddr1 vs. ddr2 63129ba616SKumar Gala */ 64129ba616SKumar Gala popts->cpo_override = 10; 65129ba616SKumar Gala 66129ba616SKumar Gala /* 67129ba616SKumar Gala * Factors to consider for write data delay: 68129ba616SKumar Gala * - number of DIMMs 69129ba616SKumar Gala * 70129ba616SKumar Gala * 1 = 1/4 clock delay 71129ba616SKumar Gala * 2 = 1/2 clock delay 72129ba616SKumar Gala * 3 = 3/4 clock delay 73129ba616SKumar Gala * 4 = 1 clock delay 74129ba616SKumar Gala * 5 = 5/4 clock delay 75129ba616SKumar Gala * 6 = 3/2 clock delay 76129ba616SKumar Gala */ 77129ba616SKumar Gala popts->write_data_delay = 5; 78129ba616SKumar Gala 79129ba616SKumar Gala /* 80129ba616SKumar Gala * Factors to consider for half-strength driver enable: 81129ba616SKumar Gala * - number of DIMMs installed 82129ba616SKumar Gala */ 83129ba616SKumar Gala popts->half_strength_driver_enable = 0; 84129ba616SKumar Gala } 85