1129ba616SKumar Gala /* 2129ba616SKumar Gala * Copyright 2008 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 4129ba616SKumar Gala * This program is free software; you can redistribute it and/or 5129ba616SKumar Gala * modify it under the terms of the GNU General Public License 6129ba616SKumar Gala * Version 2 as published by the Free Software Foundation. 7129ba616SKumar Gala */ 8129ba616SKumar Gala 9129ba616SKumar Gala #include <common.h> 10129ba616SKumar Gala 11*5614e71bSYork Sun #include <fsl_ddr_sdram.h> 12*5614e71bSYork Sun #include <fsl_ddr_dimm_params.h> 13129ba616SKumar Gala 14712cf7abSYork Sun struct board_specific_parameters { 154ca06607SHaiying Wang u32 n_ranks; 16712cf7abSYork Sun u32 datarate_mhz_high; 174ca06607SHaiying Wang u32 clk_adjust; 184ca06607SHaiying Wang u32 cpo; 194ca06607SHaiying Wang u32 write_data_delay; 200dd38a35SPriyanka Jain u32 force_2t; 21712cf7abSYork Sun }; 224ca06607SHaiying Wang 23634bc554SYork Sun /* 24712cf7abSYork Sun * This table contains all valid speeds we want to override with board 25712cf7abSYork Sun * specific parameters. datarate_mhz_high values need to be in ascending order 26712cf7abSYork Sun * for each n_ranks group. 27634bc554SYork Sun * 28634bc554SYork Sun * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been 29634bc554SYork Sun * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for 30634bc554SYork Sun * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G. 31634bc554SYork Sun * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks 32634bc554SYork Sun * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1. 33712cf7abSYork Sun * 34712cf7abSYork Sun * CPO value doesn't matter if workaround for errata 111 and 134 enabled. 354ca06607SHaiying Wang */ 36712cf7abSYork Sun static const struct board_specific_parameters udimm0[] = { 37634bc554SYork Sun /* 38634bc554SYork Sun * memory controller 0 39712cf7abSYork Sun * num| hi| clk| cpo|wrdata|2T 40712cf7abSYork Sun * ranks| mhz|adjst| | delay| 41634bc554SYork Sun */ 42712cf7abSYork Sun {2, 333, 8, 7, 5, 0}, 43712cf7abSYork Sun {2, 400, 8, 9, 5, 0}, 44712cf7abSYork Sun {2, 549, 8, 11, 5, 0}, 45712cf7abSYork Sun {2, 680, 8, 10, 5, 0}, 46712cf7abSYork Sun {2, 850, 8, 12, 5, 1}, 47712cf7abSYork Sun {1, 333, 6, 7, 3, 0}, 48712cf7abSYork Sun {1, 400, 6, 9, 3, 0}, 49712cf7abSYork Sun {1, 549, 6, 11, 3, 0}, 50712cf7abSYork Sun {1, 680, 1, 10, 5, 0}, 51712cf7abSYork Sun {1, 850, 1, 12, 5, 0}, 52712cf7abSYork Sun {} 534ca06607SHaiying Wang }; 544ca06607SHaiying Wang 55712cf7abSYork Sun static const struct board_specific_parameters udimm1[] = { 56634bc554SYork Sun /* 57634bc554SYork Sun * memory controller 1 58712cf7abSYork Sun * num| hi| clk| cpo|wrdata|2T 59712cf7abSYork Sun * ranks| mhz|adjst| | delay| 60634bc554SYork Sun */ 61712cf7abSYork Sun {2, 333, 8, 7, 5, 0}, 62712cf7abSYork Sun {2, 400, 8, 9, 5, 0}, 63712cf7abSYork Sun {2, 549, 8, 11, 5, 0}, 64712cf7abSYork Sun {2, 680, 8, 11, 5, 0}, 65712cf7abSYork Sun {2, 850, 8, 13, 5, 1}, 66712cf7abSYork Sun {1, 333, 6, 7, 3, 0}, 67712cf7abSYork Sun {1, 400, 6, 9, 3, 0}, 68712cf7abSYork Sun {1, 549, 6, 11, 3, 0}, 69712cf7abSYork Sun {1, 680, 1, 11, 6, 0}, 70712cf7abSYork Sun {1, 850, 1, 13, 6, 0}, 71712cf7abSYork Sun {} 72712cf7abSYork Sun }; 73712cf7abSYork Sun 74712cf7abSYork Sun static const struct board_specific_parameters *udimms[] = { 75712cf7abSYork Sun udimm0, 76712cf7abSYork Sun udimm1, 77712cf7abSYork Sun }; 78712cf7abSYork Sun 79712cf7abSYork Sun static const struct board_specific_parameters rdimm0[] = { 80712cf7abSYork Sun /* 81712cf7abSYork Sun * memory controller 0 82712cf7abSYork Sun * num| hi| clk| cpo|wrdata|2T 83712cf7abSYork Sun * ranks| mhz|adjst| | delay| 84712cf7abSYork Sun */ 85712cf7abSYork Sun {2, 333, 4, 7, 3, 0}, 86712cf7abSYork Sun {2, 400, 4, 9, 3, 0}, 87712cf7abSYork Sun {2, 549, 4, 11, 3, 0}, 88712cf7abSYork Sun {2, 680, 4, 10, 3, 0}, 89712cf7abSYork Sun {2, 850, 4, 12, 3, 1}, 90712cf7abSYork Sun {} 91712cf7abSYork Sun }; 92712cf7abSYork Sun 93712cf7abSYork Sun static const struct board_specific_parameters rdimm1[] = { 94712cf7abSYork Sun /* 95712cf7abSYork Sun * memory controller 1 96712cf7abSYork Sun * num| hi| clk| cpo|wrdata|2T 97712cf7abSYork Sun * ranks| mhz|adjst| | delay| 98712cf7abSYork Sun */ 99712cf7abSYork Sun {2, 333, 4, 7, 3, 0}, 100712cf7abSYork Sun {2, 400, 4, 9, 3, 0}, 101712cf7abSYork Sun {2, 549, 4, 11, 3, 0}, 102712cf7abSYork Sun {2, 680, 4, 11, 3, 0}, 103712cf7abSYork Sun {2, 850, 4, 13, 3, 1}, 104712cf7abSYork Sun {} 105712cf7abSYork Sun }; 106712cf7abSYork Sun 107712cf7abSYork Sun static const struct board_specific_parameters *rdimms[] = { 108712cf7abSYork Sun rdimm0, 109712cf7abSYork Sun rdimm1, 110634bc554SYork Sun }; 111634bc554SYork Sun 112dfb49108SHaiying Wang void fsl_ddr_board_options(memctl_options_t *popts, 113dfb49108SHaiying Wang dimm_params_t *pdimm, 114dfb49108SHaiying Wang unsigned int ctrl_num) 115129ba616SKumar Gala { 116712cf7abSYork Sun const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 1174ca06607SHaiying Wang ulong ddr_freq; 118634bc554SYork Sun 119712cf7abSYork Sun if (ctrl_num > 1) { 120712cf7abSYork Sun printf("Wrong parameter for controller number %d", ctrl_num); 121712cf7abSYork Sun return; 122712cf7abSYork Sun } 123634bc554SYork Sun if (!pdimm->n_ranks) 124634bc554SYork Sun return; 125634bc554SYork Sun 126712cf7abSYork Sun if (popts->registered_dimm_en) 127712cf7abSYork Sun pbsp = rdimms[ctrl_num]; 128712cf7abSYork Sun else 129712cf7abSYork Sun pbsp = udimms[ctrl_num]; 130129ba616SKumar Gala 1314ca06607SHaiying Wang /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 1324ca06607SHaiying Wang * freqency and n_banks specified in board_specific_parameters table. 133129ba616SKumar Gala */ 1344ca06607SHaiying Wang ddr_freq = get_ddr_freq(0) / 1000000; 135712cf7abSYork Sun while (pbsp->datarate_mhz_high) { 136712cf7abSYork Sun if (pbsp->n_ranks == pdimm->n_ranks) { 137712cf7abSYork Sun if (ddr_freq <= pbsp->datarate_mhz_high) { 1384ca06607SHaiying Wang popts->clk_adjust = pbsp->clk_adjust; 1394ca06607SHaiying Wang popts->cpo_override = pbsp->cpo; 140712cf7abSYork Sun popts->write_data_delay = 141712cf7abSYork Sun pbsp->write_data_delay; 1420dd38a35SPriyanka Jain popts->twot_en = pbsp->force_2t; 143712cf7abSYork Sun goto found; 144712cf7abSYork Sun } 145712cf7abSYork Sun pbsp_highest = pbsp; 1464ca06607SHaiying Wang } 1474ca06607SHaiying Wang pbsp++; 1484ca06607SHaiying Wang } 149129ba616SKumar Gala 150712cf7abSYork Sun if (pbsp_highest) { 151712cf7abSYork Sun printf("Error: board specific timing not found " 152712cf7abSYork Sun "for data rate %lu MT/s!\n" 153712cf7abSYork Sun "Trying to use the highest speed (%u) parameters\n", 154712cf7abSYork Sun ddr_freq, pbsp_highest->datarate_mhz_high); 155712cf7abSYork Sun popts->clk_adjust = pbsp->clk_adjust; 156712cf7abSYork Sun popts->cpo_override = pbsp->cpo; 157712cf7abSYork Sun popts->write_data_delay = pbsp->write_data_delay; 1580dd38a35SPriyanka Jain popts->twot_en = pbsp->force_2t; 159712cf7abSYork Sun } else { 160712cf7abSYork Sun panic("DIMM is not supported by this board"); 161939e5bf9SYork Sun } 162634bc554SYork Sun 163712cf7abSYork Sun found: 164129ba616SKumar Gala /* 165129ba616SKumar Gala * Factors to consider for half-strength driver enable: 166129ba616SKumar Gala * - number of DIMMs installed 167129ba616SKumar Gala */ 168129ba616SKumar Gala popts->half_strength_driver_enable = 0; 169129ba616SKumar Gala } 170