1*129ba616SKumar Gala /* 2*129ba616SKumar Gala * Copyright 2008 Freescale Semiconductor, Inc. 3*129ba616SKumar Gala * 4*129ba616SKumar Gala * This program is free software; you can redistribute it and/or 5*129ba616SKumar Gala * modify it under the terms of the GNU General Public License 6*129ba616SKumar Gala * Version 2 as published by the Free Software Foundation. 7*129ba616SKumar Gala */ 8*129ba616SKumar Gala 9*129ba616SKumar Gala #include <common.h> 10*129ba616SKumar Gala #include <i2c.h> 11*129ba616SKumar Gala 12*129ba616SKumar Gala #include <asm/fsl_ddr_sdram.h> 13*129ba616SKumar Gala 14*129ba616SKumar Gala static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) 15*129ba616SKumar Gala { 16*129ba616SKumar Gala i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); 17*129ba616SKumar Gala } 18*129ba616SKumar Gala 19*129ba616SKumar Gala unsigned int fsl_ddr_get_mem_data_rate(void) 20*129ba616SKumar Gala { 21*129ba616SKumar Gala return get_ddr_freq(0); 22*129ba616SKumar Gala } 23*129ba616SKumar Gala 24*129ba616SKumar Gala void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, 25*129ba616SKumar Gala unsigned int ctrl_num) 26*129ba616SKumar Gala { 27*129ba616SKumar Gala unsigned int i; 28*129ba616SKumar Gala unsigned int i2c_address = 0; 29*129ba616SKumar Gala 30*129ba616SKumar Gala for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 31*129ba616SKumar Gala if (ctrl_num == 0 && i == 0) { 32*129ba616SKumar Gala i2c_address = SPD_EEPROM_ADDRESS1; 33*129ba616SKumar Gala } 34*129ba616SKumar Gala if (ctrl_num == 1 && i == 0) { 35*129ba616SKumar Gala i2c_address = SPD_EEPROM_ADDRESS2; 36*129ba616SKumar Gala } 37*129ba616SKumar Gala get_spd(&(ctrl_dimms_spd[i]), i2c_address); 38*129ba616SKumar Gala } 39*129ba616SKumar Gala } 40*129ba616SKumar Gala 41*129ba616SKumar Gala void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) 42*129ba616SKumar Gala { 43*129ba616SKumar Gala /* 44*129ba616SKumar Gala * Factors to consider for clock adjust: 45*129ba616SKumar Gala * - number of chips on bus 46*129ba616SKumar Gala * - position of slot 47*129ba616SKumar Gala * - DDR1 vs. DDR2? 48*129ba616SKumar Gala * - ??? 49*129ba616SKumar Gala * 50*129ba616SKumar Gala * This needs to be determined on a board-by-board basis. 51*129ba616SKumar Gala * 0110 3/4 cycle late 52*129ba616SKumar Gala * 0111 7/8 cycle late 53*129ba616SKumar Gala */ 54*129ba616SKumar Gala popts->clk_adjust = 7; 55*129ba616SKumar Gala 56*129ba616SKumar Gala /* 57*129ba616SKumar Gala * Factors to consider for CPO: 58*129ba616SKumar Gala * - frequency 59*129ba616SKumar Gala * - ddr1 vs. ddr2 60*129ba616SKumar Gala */ 61*129ba616SKumar Gala popts->cpo_override = 10; 62*129ba616SKumar Gala 63*129ba616SKumar Gala /* 64*129ba616SKumar Gala * Factors to consider for write data delay: 65*129ba616SKumar Gala * - number of DIMMs 66*129ba616SKumar Gala * 67*129ba616SKumar Gala * 1 = 1/4 clock delay 68*129ba616SKumar Gala * 2 = 1/2 clock delay 69*129ba616SKumar Gala * 3 = 3/4 clock delay 70*129ba616SKumar Gala * 4 = 1 clock delay 71*129ba616SKumar Gala * 5 = 5/4 clock delay 72*129ba616SKumar Gala * 6 = 3/2 clock delay 73*129ba616SKumar Gala */ 74*129ba616SKumar Gala popts->write_data_delay = 5; 75*129ba616SKumar Gala 76*129ba616SKumar Gala /* 77*129ba616SKumar Gala * Factors to consider for half-strength driver enable: 78*129ba616SKumar Gala * - number of DIMMs installed 79*129ba616SKumar Gala */ 80*129ba616SKumar Gala popts->half_strength_driver_enable = 0; 81*129ba616SKumar Gala } 82