1 /*
2  * Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * (C) Copyright 2000
5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25 
26 #include <common.h>
27 #include <asm/mmu.h>
28 
29 struct fsl_e_tlb_entry tlb_table[] = {
30 	/* TLB 0 - for temp stack in cache */
31 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
32 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
33 		      0, 0, BOOKE_PAGESZ_4K, 0),
34 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
35 		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
36 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
37 		      0, 0, BOOKE_PAGESZ_4K, 0),
38 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
39 		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
40 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
41 		      0, 0, BOOKE_PAGESZ_4K, 0),
42 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
43 		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
44 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
45 		      0, 0, BOOKE_PAGESZ_4K, 0),
46 
47 	/* TLB 1 Initializations */
48 	/*
49 	 * TLBe 0:	64M	Non-cacheable, guarded
50 	 * Out of reset this entry is only 4K.
51 	 * 0xfc000000	256K	NAND FLASH (CS3)
52 	 * 0xfe000000	32M	NOR FLASH (CS0)
53 	 */
54 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
55 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
56 		      0, 0, BOOKE_PAGESZ_64M, 1),
57 
58 	/*
59 	 * TLBe 1:	256KB	Non-cacheable, guarded
60 	 * 0xf8000000	32K	BCSR
61 	 * 0xf8008000	32K	PIB (CS4)
62 	 * 0xf8010000	32K	PIB (CS5)
63 	 */
64 	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
65 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
66 		      0, 1, BOOKE_PAGESZ_256K, 1),
67 
68 	/*
69 	 * TLBe 2:	256M	Non-cacheable, guarded
70 	 * 0xa00000000	256M	PCIe MEM (lower half)
71 	 */
72 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
73 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
74 		      0, 2, BOOKE_PAGESZ_256M, 1),
75 
76 	/*
77 	 * TLBe 3:	256M	Non-cacheable, guarded
78 	 * 0xb00000000	256M	PCIe MEM (higher half)
79 	 */
80 	SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
81 		      (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
82 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 		      0, 3, BOOKE_PAGESZ_256M, 1),
84 
85 	/*
86 	 * TLBe 4:	64M	Non-cacheable, guarded
87 	 * 0xe000_0000	1M	CCSRBAR
88 	 * 0xe280_0000	8M	PCIe IO
89 	 */
90 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
91 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
92 		      0, 4, BOOKE_PAGESZ_64M, 1),
93 };
94 
95 int num_tlb_entries = ARRAY_SIZE(tlb_table);
96