1 /*
2  * Copyright 2009-2010 Freescale Semiconductor.
3  *
4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #include <common.h>
26 #include <hwconfig.h>
27 #include <pci.h>
28 #include <asm/processor.h>
29 #include <asm/mmu.h>
30 #include <asm/cache.h>
31 #include <asm/immap_85xx.h>
32 #include <asm/fsl_pci.h>
33 #include <asm/fsl_ddr_sdram.h>
34 #include <asm/fsl_serdes.h>
35 #include <asm/io.h>
36 #include <spd_sdram.h>
37 #include <i2c.h>
38 #include <ioports.h>
39 #include <libfdt.h>
40 #include <fdt_support.h>
41 #include <fsl_esdhc.h>
42 #include <phy.h>
43 
44 #include "bcsr.h"
45 #if defined(CONFIG_PQ_MDS_PIB)
46 #include "../common/pq-mds-pib.h"
47 #endif
48 
49 const qe_iop_conf_t qe_iop_conf_tab[] = {
50 	/* QE_MUX_MDC */
51 	{2,  31, 1, 0, 1}, /* QE_MUX_MDC               */
52 
53 	/* QE_MUX_MDIO */
54 	{2,  30, 3, 0, 2}, /* QE_MUX_MDIO              */
55 
56 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
57 	/* UCC_1_RGMII */
58 	{2, 11, 2, 0, 1}, /* CLK12 */
59 	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
60 	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
61 	{0,  2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2      */
62 	{0,  3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
63 	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
64 	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
65 	{0,  8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
66 	{0,  9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
67 	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
68 	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
69 	{2,  8, 2, 0, 1}, /* ENET1_GRXCLK              */
70 	{2, 20, 1, 0, 2}, /* ENET1_GTXCLK              */
71 
72 	/* UCC_2_RGMII */
73 	{2, 16, 2, 0, 3}, /* CLK17 */
74 	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
75 	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
76 	{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2      */
77 	{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3      */
78 	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
79 	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
80 	{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2      */
81 	{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3      */
82 	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
83 	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
84 	{2,  3, 2, 0, 1}, /* ENET2_GRXCLK              */
85 	{2,  2, 1, 0, 2}, /* ENET2_GTXCLK              */
86 
87 	/* UCC_3_RGMII */
88 	{2, 11, 2, 0, 1}, /* CLK12 */
89 	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
90 	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
91 	{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2      */
92 	{1,  0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3      */
93 	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
94 	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
95 	{1,  5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2      */
96 	{1,  6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3      */
97 	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
98 	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
99 	{2,  9, 2, 0, 2}, /* ENET3_GRXCLK              */
100 	{2, 25, 1, 0, 2}, /* ENET3_GTXCLK              */
101 
102 	/* UCC_4_RGMII */
103 	{2, 16, 2, 0, 3}, /* CLK17 */
104 	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
105 	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
106 	{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2      */
107 	{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3      */
108 	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
109 	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
110 	{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2      */
111 	{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3      */
112 	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
113 	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
114 	{2, 17, 2, 0, 2}, /* ENET4_GRXCLK              */
115 	{2, 24, 1, 0, 2}, /* ENET4_GTXCLK              */
116 
117 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
118 	/* UCC_1_RMII */
119 	{2, 15, 2, 0, 1}, /* CLK16 */
120 	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
121 	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
122 	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
123 	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
124 	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
125 	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
126 
127 	/* UCC_2_RMII */
128 	{2, 15, 2, 0, 1}, /* CLK16 */
129 	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
130 	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
131 	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
132 	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
133 	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
134 	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
135 
136 	/* UCC_3_RMII */
137 	{2, 15, 2, 0, 1}, /* CLK16 */
138 	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
139 	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
140 	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
141 	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
142 	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
143 	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
144 
145 	/* UCC_4_RMII */
146 	{2, 15, 2, 0, 1}, /* CLK16 */
147 	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
148 	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
149 	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
150 	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
151 	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
152 	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
153 #endif
154 
155 	/* UART1 is muxed with QE PortF bit [9-12].*/
156 	{5, 12, 2, 0, 3}, /* UART1_SIN */
157 	{5, 9,  1, 0, 3}, /* UART1_SOUT */
158 	{5, 10, 2, 0, 3}, /* UART1_CTS_B */
159 	{5, 11, 1, 0, 2}, /* UART1_RTS_B */
160 
161 	/* QE UART                                     */
162 	{0, 19, 1, 0, 2}, /* QEUART_TX                 */
163 	{1, 17, 2, 0, 3}, /* QEUART_RX                 */
164 	{0, 25, 1, 0, 1}, /* QEUART_RTS                */
165 	{1, 23, 2, 0, 1}, /* QEUART_CTS                */
166 
167 	/* QE USB                                      */
168 	{5,  3, 1, 0, 1}, /* USB_OE                    */
169 	{5,  4, 1, 0, 2}, /* USB_TP                    */
170 	{5,  5, 1, 0, 2}, /* USB_TN                    */
171 	{5,  6, 2, 0, 2}, /* USB_RP                    */
172 	{5,  7, 2, 0, 1}, /* USB_RX                    */
173 	{5,  8, 2, 0, 1}, /* USB_RN                    */
174 	{2,  4, 2, 0, 2}, /* CLK5                      */
175 
176 	/* SPI Flash, M25P40                           */
177 	{4, 27, 3, 0, 1}, /* SPI_MOSI                  */
178 	{4, 28, 3, 0, 1}, /* SPI_MISO                  */
179 	{4, 29, 3, 0, 1}, /* SPI_CLK                   */
180 	{4, 30, 1, 0, 0}, /* SPI_SEL, GPIO             */
181 
182 	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
183 };
184 
185 void local_bus_init(void);
186 
187 int board_early_init_f (void)
188 {
189 	/*
190 	 * Initialize local bus.
191 	 */
192 	local_bus_init ();
193 
194 	enable_8569mds_flash_write();
195 
196 #ifdef CONFIG_QE
197 	enable_8569mds_qe_uec();
198 #endif
199 
200 #if CONFIG_SYS_I2C2_OFFSET
201 	/* Enable I2C2 signals instead of SD signals */
202 	volatile struct ccsr_gur *gur;
203 	gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
204 	gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
205 	gur->plppar1 |= PLPPAR1_I2C2_VAL;
206 	gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
207 	gur->plpdir1 |= PLPDIR1_I2C2_VAL;
208 
209 	disable_8569mds_brd_eeprom_write_protect();
210 #endif
211 
212 	return 0;
213 }
214 
215 int board_early_init_r(void)
216 {
217 	const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
218 	const u8 flash_esel = 0;
219 
220 	/*
221 	 * Remap Boot flash to caching-inhibited
222 	 * so that flash can be erased properly.
223 	 */
224 
225 	/* Flush d-cache and invalidate i-cache of any FLASH data */
226 	flush_dcache();
227 	invalidate_icache();
228 
229 	/* invalidate existing TLB entry for flash */
230 	disable_tlb(flash_esel);
231 
232 	set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE,	/* tlb, epn, rpn */
233 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
234 		0, flash_esel,				/* ts, esel */
235 		BOOKE_PAGESZ_64M, 1);			/* tsize, iprot */
236 
237 	return 0;
238 }
239 
240 int checkboard (void)
241 {
242 	printf ("Board: 8569 MDS\n");
243 
244 	return 0;
245 }
246 
247 #if !defined(CONFIG_SPD_EEPROM)
248 phys_size_t fixed_sdram(void)
249 {
250 	volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
251 	uint d_init;
252 
253 	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
254 	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
255 	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
256 	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
257 	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
258 	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
259 	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
260 	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
261 	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
262 	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
263 	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
264 	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
265 	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
266 	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
267 	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
268 	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
269 	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
270 	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
271 #if defined (CONFIG_DDR_ECC)
272 	out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
273 	out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
274 	out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
275 #endif
276 	udelay(500);
277 
278 	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
279 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
280 	d_init = 1;
281 	debug("DDR - 1st controller: memory initializing\n");
282 	/*
283 	 * Poll until memory is initialized.
284 	 * 512 Meg at 400 might hit this 200 times or so.
285 	 */
286 	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
287 		udelay(1000);
288 	}
289 	debug("DDR: memory initialized\n\n");
290 	udelay(500);
291 #endif
292 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
293 }
294 #endif
295 
296 /*
297  * Initialize Local Bus
298  */
299 void
300 local_bus_init(void)
301 {
302 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
303 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
304 
305 	uint clkdiv;
306 	uint lbc_hz;
307 	sys_info_t sysinfo;
308 
309 	get_sys_info(&sysinfo);
310 	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
311 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
312 
313 	out_be32(&gur->lbiuiplldcr1, 0x00078080);
314 	if (clkdiv == 16)
315 		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
316 	else if (clkdiv == 8)
317 		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
318 	else if (clkdiv == 4)
319 		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
320 
321 	out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
322 }
323 
324 static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
325 {
326 	const char *status = "disabled";
327 	int off;
328 	int err;
329 
330 	off = fdt_path_offset(blob, alias);
331 	if (off < 0) {
332 		printf("WARNING: could not find %s alias: %s.\n", alias,
333 			fdt_strerror(off));
334 		return;
335 	}
336 
337 	err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
338 	if (err) {
339 		printf("WARNING: could not set status for serial0: %s.\n",
340 			fdt_strerror(err));
341 		return;
342 	}
343 }
344 
345 /*
346  * Because of an erratum in prototype boards it is impossible to use eSDHC
347  * without disabling UART0 (which makes it quite easy to 'brick' the board
348  * by simply issung 'setenv hwconfig esdhc', and not able to interact with
349  * U-Boot anylonger).
350  *
351  * So, but default we assume that the board is a prototype, which is a most
352  * safe assumption. There is no way to determine board revision from a
353  * register, so we use hwconfig.
354  */
355 
356 static int prototype_board(void)
357 {
358 	if (hwconfig_subarg("board", "rev", NULL))
359 		return hwconfig_subarg_cmp("board", "rev", "prototype");
360 	return 1;
361 }
362 
363 static int esdhc_disables_uart0(void)
364 {
365 	return prototype_board() ||
366 	       hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
367 }
368 
369 static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
370 {
371 	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
372 	const char *devtype = "serial";
373 	const char *compat = "ucc_uart";
374 	const char *clk = "brg9";
375 	u32 portnum = 0;
376 	int off = -1;
377 
378 	if (!hwconfig("qe_uart"))
379 		return;
380 
381 	if (hwconfig("esdhc") && esdhc_disables_uart0()) {
382 		printf("QE UART: won't enable with esdhc.\n");
383 		return;
384 	}
385 
386 	fdt_board_disable_serial(blob, bd, "serial1");
387 
388 	while (1) {
389 		const u32 *idx;
390 		int len;
391 
392 		off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
393 		if (off < 0) {
394 			printf("WARNING: unable to fixup device tree for "
395 				"QE UART\n");
396 			return;
397 		}
398 
399 		idx = fdt_getprop(blob, off, "cell-index", &len);
400 		if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
401 			continue;
402 		break;
403 	}
404 
405 	fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
406 	fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
407 	fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
408 	fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
409 	fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
410 
411 	setbits_8(&bcsr[15], BCSR15_QEUART_EN);
412 }
413 
414 #ifdef CONFIG_FSL_ESDHC
415 
416 int board_mmc_init(bd_t *bd)
417 {
418 	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
419 	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
420 	u8 bcsr6 = BCSR6_SD_CARD_1BIT;
421 
422 	if (!hwconfig("esdhc"))
423 		return 0;
424 
425 	printf("Enabling eSDHC...\n"
426 	       "  For eSDHC to function, I2C2 ");
427 	if (esdhc_disables_uart0()) {
428 		printf("and UART0 should be disabled.\n");
429 		printf("  Redirecting stderr, stdout and stdin to UART1...\n");
430 		console_assign(stderr, "eserial1");
431 		console_assign(stdout, "eserial1");
432 		console_assign(stdin, "eserial1");
433 		printf("Switched to UART1 (initial log has been printed to "
434 		       "UART0).\n");
435 
436 		clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
437 					       PLPPAR1_ESDHC_4BITS_VAL);
438 		clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
439 					       PLPDIR1_ESDHC_4BITS_VAL);
440 		bcsr6 |= BCSR6_SD_CARD_4BITS;
441 	} else {
442 		printf("should be disabled.\n");
443 	}
444 
445 	/* Assign I2C2 signals to eSDHC. */
446 	clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
447 				       PLPPAR1_ESDHC_VAL);
448 	clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
449 				       PLPDIR1_ESDHC_VAL);
450 
451 	/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
452 	setbits_8(&bcsr[6], bcsr6);
453 
454 	return fsl_esdhc_mmc_init(bd);
455 }
456 
457 static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
458 {
459 	const char *status = "disabled";
460 	int off = -1;
461 
462 	if (!hwconfig("esdhc"))
463 		return;
464 
465 	if (esdhc_disables_uart0())
466 		fdt_board_disable_serial(blob, bd, "serial0");
467 
468 	while (1) {
469 		const u32 *idx;
470 		int len;
471 
472 		off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
473 		if (off < 0)
474 			break;
475 
476 		idx = fdt_getprop(blob, off, "cell-index", &len);
477 		if (!idx || len != sizeof(*idx))
478 			continue;
479 
480 		if (*idx == 1) {
481 			fdt_setprop(blob, off, "status", status,
482 				    strlen(status) + 1);
483 			break;
484 		}
485 	}
486 
487 	if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
488 		off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
489 		if (off < 0) {
490 			printf("WARNING: could not find esdhc node\n");
491 			return;
492 		}
493 		fdt_delprop(blob, off, "sdhci,1-bit-only");
494 	}
495 }
496 #else
497 static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
498 #endif
499 
500 static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
501 {
502 	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
503 
504 	if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
505 		clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
506 	else
507 		setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
508 
509 	if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
510 		clrbits_8(&bcsr[17], BCSR17_USBVCC);
511 		clrbits_8(&bcsr[17], BCSR17_USBMODE);
512 		do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
513 				   "peripheral", sizeof("peripheral"), 1);
514 	} else {
515 		setbits_8(&bcsr[17], BCSR17_USBVCC);
516 		setbits_8(&bcsr[17], BCSR17_USBMODE);
517 	}
518 
519 	clrbits_8(&bcsr[17], BCSR17_nUSBEN);
520 }
521 
522 #ifdef CONFIG_PCI
523 void pci_init_board(void)
524 {
525 #if defined(CONFIG_PQ_MDS_PIB)
526 	pib_init();
527 #endif
528 
529 	fsl_pcie_init_board(0);
530 }
531 #endif /* CONFIG_PCI */
532 
533 #if defined(CONFIG_OF_BOARD_SETUP)
534 void ft_board_setup(void *blob, bd_t *bd)
535 {
536 #if defined(CONFIG_SYS_UCC_RMII_MODE)
537 	int nodeoff, off, err;
538 	unsigned int val;
539 	const u32 *ph;
540 	const u32 *index;
541 
542 	/* fixup device tree for supporting rmii mode */
543 	nodeoff = -1;
544 	while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
545 				"ucc_geth")) >= 0) {
546 		err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
547 						"clk16");
548 		if (err < 0) {
549 			printf("WARNING: could not set tx-clock-name %s.\n",
550 				fdt_strerror(err));
551 			break;
552 		}
553 
554 		err = fdt_fixup_phy_connection(blob, nodeoff,
555 				PHY_INTERFACE_MODE_RMII);
556 
557 		if (err < 0) {
558 			printf("WARNING: could not set phy-connection-type "
559 				"%s.\n", fdt_strerror(err));
560 			break;
561 		}
562 
563 		index = fdt_getprop(blob, nodeoff, "cell-index", 0);
564 		if (index == NULL) {
565 			printf("WARNING: could not get cell-index of ucc\n");
566 			break;
567 		}
568 
569 		ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
570 		if (ph == NULL) {
571 			printf("WARNING: could not get phy-handle of ucc\n");
572 			break;
573 		}
574 
575 		off = fdt_node_offset_by_phandle(blob, *ph);
576 		if (off < 0) {
577 			printf("WARNING: could not get phy node	%s.\n",
578 				fdt_strerror(err));
579 			break;
580 		}
581 
582 		val = 0x7 + *index; /* RMII phy address starts from 0x8 */
583 
584 		err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
585 		if (err < 0) {
586 			printf("WARNING: could not set reg for phy-handle "
587 				"%s.\n", fdt_strerror(err));
588 			break;
589 		}
590 	}
591 #endif
592 	ft_cpu_setup(blob, bd);
593 
594 	FT_FSL_PCI_SETUP;
595 
596 	fdt_board_fixup_esdhc(blob, bd);
597 	fdt_board_fixup_qe_uart(blob, bd);
598 	fdt_board_fixup_qe_usb(blob, bd);
599 }
600 #endif
601