1 /* 2 * Copyright 2009 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/mmu.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd_sdram.h> 34 #include <i2c.h> 35 #include <ioports.h> 36 #include <libfdt.h> 37 #include <fdt_support.h> 38 39 #include "bcsr.h" 40 41 phys_size_t fixed_sdram(void); 42 43 const qe_iop_conf_t qe_iop_conf_tab[] = { 44 /* QE_MUX_MDC */ 45 {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ 46 47 /* QE_MUX_MDIO */ 48 {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */ 49 50 /* UCC_1_RGMII */ 51 {2, 11, 2, 0, 1}, /* CLK12 */ 52 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ 53 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ 54 {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */ 55 {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ 56 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ 57 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ 58 {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ 59 {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ 60 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 61 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ 62 {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */ 63 {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */ 64 65 /* UCC_2_RGMII */ 66 {2, 16, 2, 0, 3}, /* CLK17 */ 67 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ 68 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ 69 {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */ 70 {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */ 71 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ 72 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ 73 {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */ 74 {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */ 75 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ 76 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ 77 {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */ 78 {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */ 79 80 /* UART1 is muxed with QE PortF bit [9-12].*/ 81 {5, 12, 2, 0, 3}, /* UART1_SIN */ 82 {5, 9, 1, 0, 3}, /* UART1_SOUT */ 83 {5, 10, 2, 0, 3}, /* UART1_CTS_B */ 84 {5, 11, 1, 0, 2}, /* UART1_RTS_B */ 85 86 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ 87 }; 88 89 void local_bus_init(void); 90 91 int board_early_init_f (void) 92 { 93 /* 94 * Initialize local bus. 95 */ 96 local_bus_init (); 97 98 enable_8569mds_flash_write(); 99 100 #ifdef CONFIG_QE 101 enable_8569mds_qe_mdio(); 102 #endif 103 104 #if CONFIG_SYS_I2C2_OFFSET 105 /* Enable I2C2 signals instead of SD signals */ 106 volatile struct ccsr_gur *gur; 107 gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000); 108 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; 109 gur->plppar1 |= PLPPAR1_I2C2_VAL; 110 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK; 111 gur->plpdir1 |= PLPDIR1_I2C2_VAL; 112 113 disable_8569mds_brd_eeprom_write_protect(); 114 #endif 115 116 return 0; 117 } 118 119 int checkboard (void) 120 { 121 printf ("Board: 8569 MDS\n"); 122 123 return 0; 124 } 125 126 phys_size_t 127 initdram(int board_type) 128 { 129 long dram_size = 0; 130 131 puts("Initializing\n"); 132 133 #if defined(CONFIG_DDR_DLL) 134 /* 135 * Work around to stabilize DDR DLL MSYNC_IN. 136 * Errata DDR9 seems to have been fixed. 137 * This is now the workaround for Errata DDR11: 138 * Override DLL = 1, Course Adj = 1, Tap Select = 0 139 */ 140 volatile ccsr_gur_t *gur = 141 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 142 143 out_be32(&gur->ddrdllcr, 0x81000000); 144 udelay(200); 145 #endif 146 147 #ifdef CONFIG_SPD_EEPROM 148 dram_size = fsl_ddr_sdram(); 149 #else 150 dram_size = fixed_sdram(); 151 #endif 152 153 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 154 dram_size *= 0x100000; 155 156 puts(" DDR: "); 157 return dram_size; 158 } 159 160 #if !defined(CONFIG_SPD_EEPROM) 161 phys_size_t fixed_sdram(void) 162 { 163 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; 164 uint d_init; 165 166 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); 167 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); 168 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 169 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 170 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 171 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 172 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 173 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 174 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); 175 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); 176 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL); 177 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); 178 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); 179 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); 180 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); 181 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); 182 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); 183 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 184 #if defined (CONFIG_DDR_ECC) 185 out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN); 186 out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS); 187 out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE); 188 #endif 189 udelay(500); 190 191 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 192 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 193 d_init = 1; 194 debug("DDR - 1st controller: memory initializing\n"); 195 /* 196 * Poll until memory is initialized. 197 * 512 Meg at 400 might hit this 200 times or so. 198 */ 199 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 200 udelay(1000); 201 } 202 debug("DDR: memory initialized\n\n"); 203 udelay(500); 204 #endif 205 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 206 } 207 #endif 208 209 /* 210 * Initialize Local Bus 211 */ 212 void 213 local_bus_init(void) 214 { 215 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 216 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 217 218 uint clkdiv; 219 uint lbc_hz; 220 sys_info_t sysinfo; 221 222 get_sys_info(&sysinfo); 223 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 224 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 225 226 out_be32(&gur->lbiuiplldcr1, 0x00078080); 227 if (clkdiv == 16) 228 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); 229 else if (clkdiv == 8) 230 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); 231 else if (clkdiv == 4) 232 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); 233 234 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); 235 } 236 237 #ifdef CONFIG_PCIE1 238 static struct pci_controller pcie1_hose; 239 #endif /* CONFIG_PCIE1 */ 240 241 int first_free_busno = 0; 242 243 #ifdef CONFIG_PCI 244 void 245 pci_init_board(void) 246 { 247 volatile ccsr_gur_t *gur; 248 uint io_sel; 249 uint host_agent; 250 251 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 252 io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 253 host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 254 255 #ifdef CONFIG_PCIE1 256 { 257 volatile ccsr_fsl_pci_t *pci; 258 struct pci_controller *hose; 259 int pcie_ep; 260 struct pci_region *r; 261 int pcie_configured; 262 263 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 264 hose = &pcie1_hose; 265 pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 266 r = hose->regions; 267 pcie_configured = io_sel >= 1; 268 269 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 270 printf ("\n PCIE connected to slot as %s (base address %x)", 271 pcie_ep ? "End Point" : "Root Complex", 272 (uint)pci); 273 274 if (pci->pme_msg_det) { 275 pci->pme_msg_det = 0xffffffff; 276 debug (" with errors. Clearing. Now 0x%08x", 277 pci->pme_msg_det); 278 } 279 printf ("\n"); 280 281 /* inbound */ 282 r += fsl_pci_setup_inbound_windows(r); 283 284 /* outbound memory */ 285 pci_set_region(r++, 286 CONFIG_SYS_PCIE1_MEM_BUS, 287 CONFIG_SYS_PCIE1_MEM_PHYS, 288 CONFIG_SYS_PCIE1_MEM_SIZE, 289 PCI_REGION_MEM); 290 291 /* outbound io */ 292 pci_set_region(r++, 293 CONFIG_SYS_PCIE1_IO_BUS, 294 CONFIG_SYS_PCIE1_IO_PHYS, 295 CONFIG_SYS_PCIE1_IO_SIZE, 296 PCI_REGION_IO); 297 298 hose->region_count = r - hose->regions; 299 300 hose->first_busno=first_free_busno; 301 pci_setup_indirect(hose, (int) &pci->cfg_addr, 302 (int) &pci->cfg_data); 303 304 fsl_pci_init(hose); 305 printf ("PCIE on bus %02x - %02x\n", 306 hose->first_busno,hose->last_busno); 307 308 first_free_busno=hose->last_busno+1; 309 310 } else { 311 printf (" PCIE: disabled\n"); 312 } 313 } 314 #else 315 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 316 #endif 317 } 318 #endif /* CONFIG_PCI */ 319 320 #if defined(CONFIG_OF_BOARD_SETUP) 321 void ft_board_setup(void *blob, bd_t *bd) 322 { 323 ft_cpu_setup(blob, bd); 324 325 #ifdef CONFIG_PCIE1 326 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 327 #endif 328 } 329 #endif 330