1 /* 2 * Copyright 2009 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <hwconfig.h> 27 #include <pci.h> 28 #include <asm/processor.h> 29 #include <asm/mmu.h> 30 #include <asm/immap_85xx.h> 31 #include <asm/fsl_pci.h> 32 #include <asm/fsl_ddr_sdram.h> 33 #include <asm/io.h> 34 #include <spd_sdram.h> 35 #include <i2c.h> 36 #include <ioports.h> 37 #include <libfdt.h> 38 #include <fdt_support.h> 39 #include <fsl_esdhc.h> 40 41 #include "bcsr.h" 42 43 phys_size_t fixed_sdram(void); 44 45 const qe_iop_conf_t qe_iop_conf_tab[] = { 46 /* QE_MUX_MDC */ 47 {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ 48 49 /* QE_MUX_MDIO */ 50 {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */ 51 52 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 53 /* UCC_1_RGMII */ 54 {2, 11, 2, 0, 1}, /* CLK12 */ 55 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ 56 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ 57 {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */ 58 {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ 59 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ 60 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ 61 {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ 62 {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ 63 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 64 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ 65 {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */ 66 {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */ 67 68 /* UCC_2_RGMII */ 69 {2, 16, 2, 0, 3}, /* CLK17 */ 70 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ 71 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ 72 {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */ 73 {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */ 74 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ 75 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ 76 {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */ 77 {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */ 78 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ 79 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ 80 {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */ 81 {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */ 82 83 /* UCC_3_RGMII */ 84 {2, 11, 2, 0, 1}, /* CLK12 */ 85 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ 86 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ 87 {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */ 88 {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */ 89 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ 90 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ 91 {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */ 92 {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */ 93 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ 94 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ 95 {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */ 96 {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */ 97 98 /* UCC_4_RGMII */ 99 {2, 16, 2, 0, 3}, /* CLK17 */ 100 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ 101 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ 102 {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */ 103 {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */ 104 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ 105 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ 106 {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */ 107 {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */ 108 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ 109 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ 110 {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */ 111 {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */ 112 113 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 114 /* UCC_1_RMII */ 115 {2, 15, 2, 0, 1}, /* CLK16 */ 116 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ 117 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ 118 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ 119 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ 120 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 121 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ 122 123 /* UCC_2_RMII */ 124 {2, 15, 2, 0, 1}, /* CLK16 */ 125 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ 126 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ 127 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ 128 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ 129 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ 130 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ 131 132 /* UCC_3_RMII */ 133 {2, 15, 2, 0, 1}, /* CLK16 */ 134 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ 135 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ 136 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ 137 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ 138 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ 139 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ 140 141 /* UCC_4_RMII */ 142 {2, 15, 2, 0, 1}, /* CLK16 */ 143 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ 144 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ 145 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ 146 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ 147 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ 148 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ 149 #endif 150 151 /* UART1 is muxed with QE PortF bit [9-12].*/ 152 {5, 12, 2, 0, 3}, /* UART1_SIN */ 153 {5, 9, 1, 0, 3}, /* UART1_SOUT */ 154 {5, 10, 2, 0, 3}, /* UART1_CTS_B */ 155 {5, 11, 1, 0, 2}, /* UART1_RTS_B */ 156 157 /* QE UART */ 158 {0, 19, 1, 0, 2}, /* QEUART_TX */ 159 {1, 17, 2, 0, 3}, /* QEUART_RX */ 160 {0, 25, 1, 0, 1}, /* QEUART_RTS */ 161 {1, 23, 2, 0, 1}, /* QEUART_CTS */ 162 163 /* QE USB */ 164 {5, 3, 1, 0, 1}, /* USB_OE */ 165 {5, 4, 1, 0, 2}, /* USB_TP */ 166 {5, 5, 1, 0, 2}, /* USB_TN */ 167 {5, 6, 2, 0, 2}, /* USB_RP */ 168 {5, 7, 2, 0, 1}, /* USB_RX */ 169 {5, 8, 2, 0, 1}, /* USB_RN */ 170 {2, 4, 2, 0, 2}, /* CLK5 */ 171 172 /* SPI Flash, M25P40 */ 173 {4, 27, 3, 0, 1}, /* SPI_MOSI */ 174 {4, 28, 3, 0, 1}, /* SPI_MISO */ 175 {4, 29, 3, 0, 1}, /* SPI_CLK */ 176 {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */ 177 178 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ 179 }; 180 181 void local_bus_init(void); 182 183 int board_early_init_f (void) 184 { 185 /* 186 * Initialize local bus. 187 */ 188 local_bus_init (); 189 190 enable_8569mds_flash_write(); 191 192 #ifdef CONFIG_QE 193 enable_8569mds_qe_uec(); 194 #endif 195 196 #if CONFIG_SYS_I2C2_OFFSET 197 /* Enable I2C2 signals instead of SD signals */ 198 volatile struct ccsr_gur *gur; 199 gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000); 200 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; 201 gur->plppar1 |= PLPPAR1_I2C2_VAL; 202 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK; 203 gur->plpdir1 |= PLPDIR1_I2C2_VAL; 204 205 disable_8569mds_brd_eeprom_write_protect(); 206 #endif 207 208 return 0; 209 } 210 211 int checkboard (void) 212 { 213 printf ("Board: 8569 MDS\n"); 214 215 return 0; 216 } 217 218 phys_size_t 219 initdram(int board_type) 220 { 221 long dram_size = 0; 222 223 puts("Initializing\n"); 224 225 #if defined(CONFIG_DDR_DLL) 226 /* 227 * Work around to stabilize DDR DLL MSYNC_IN. 228 * Errata DDR9 seems to have been fixed. 229 * This is now the workaround for Errata DDR11: 230 * Override DLL = 1, Course Adj = 1, Tap Select = 0 231 */ 232 volatile ccsr_gur_t *gur = 233 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 234 235 out_be32(&gur->ddrdllcr, 0x81000000); 236 udelay(200); 237 #endif 238 239 #ifdef CONFIG_SPD_EEPROM 240 dram_size = fsl_ddr_sdram(); 241 #else 242 dram_size = fixed_sdram(); 243 #endif 244 245 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 246 dram_size *= 0x100000; 247 248 puts(" DDR: "); 249 return dram_size; 250 } 251 252 #if !defined(CONFIG_SPD_EEPROM) 253 phys_size_t fixed_sdram(void) 254 { 255 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; 256 uint d_init; 257 258 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); 259 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); 260 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 261 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 262 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 263 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 264 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 265 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 266 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); 267 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); 268 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL); 269 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); 270 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); 271 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); 272 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); 273 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); 274 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); 275 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 276 #if defined (CONFIG_DDR_ECC) 277 out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN); 278 out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS); 279 out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE); 280 #endif 281 udelay(500); 282 283 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 284 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 285 d_init = 1; 286 debug("DDR - 1st controller: memory initializing\n"); 287 /* 288 * Poll until memory is initialized. 289 * 512 Meg at 400 might hit this 200 times or so. 290 */ 291 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 292 udelay(1000); 293 } 294 debug("DDR: memory initialized\n\n"); 295 udelay(500); 296 #endif 297 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 298 } 299 #endif 300 301 /* 302 * Initialize Local Bus 303 */ 304 void 305 local_bus_init(void) 306 { 307 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 308 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 309 310 uint clkdiv; 311 uint lbc_hz; 312 sys_info_t sysinfo; 313 314 get_sys_info(&sysinfo); 315 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 316 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 317 318 out_be32(&gur->lbiuiplldcr1, 0x00078080); 319 if (clkdiv == 16) 320 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); 321 else if (clkdiv == 8) 322 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); 323 else if (clkdiv == 4) 324 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); 325 326 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); 327 } 328 329 static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias) 330 { 331 const char *status = "disabled"; 332 int off; 333 int err; 334 335 off = fdt_path_offset(blob, alias); 336 if (off < 0) { 337 printf("WARNING: could not find %s alias: %s.\n", alias, 338 fdt_strerror(off)); 339 return; 340 } 341 342 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); 343 if (err) { 344 printf("WARNING: could not set status for serial0: %s.\n", 345 fdt_strerror(err)); 346 return; 347 } 348 } 349 350 /* 351 * Because of an erratum in prototype boards it is impossible to use eSDHC 352 * without disabling UART0 (which makes it quite easy to 'brick' the board 353 * by simply issung 'setenv hwconfig esdhc', and not able to interact with 354 * U-Boot anylonger). 355 * 356 * So, but default we assume that the board is a prototype, which is a most 357 * safe assumption. There is no way to determine board revision from a 358 * register, so we use hwconfig. 359 */ 360 361 static int prototype_board(void) 362 { 363 if (hwconfig_subarg("board", "rev", NULL)) 364 return hwconfig_subarg_cmp("board", "rev", "prototype"); 365 return 1; 366 } 367 368 static int esdhc_disables_uart0(void) 369 { 370 return prototype_board() || 371 hwconfig_subarg_cmp("esdhc", "mode", "4-bits"); 372 } 373 374 static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd) 375 { 376 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; 377 const char *devtype = "serial"; 378 const char *compat = "ucc_uart"; 379 const char *clk = "brg9"; 380 u32 portnum = 0; 381 int off = -1; 382 383 if (!hwconfig("qe_uart")) 384 return; 385 386 if (hwconfig("esdhc") && esdhc_disables_uart0()) { 387 printf("QE UART: won't enable with esdhc.\n"); 388 return; 389 } 390 391 fdt_board_disable_serial(blob, bd, "serial1"); 392 393 while (1) { 394 const u32 *idx; 395 int len; 396 397 off = fdt_node_offset_by_compatible(blob, off, "ucc_geth"); 398 if (off < 0) { 399 printf("WARNING: unable to fixup device tree for " 400 "QE UART\n"); 401 return; 402 } 403 404 idx = fdt_getprop(blob, off, "cell-index", &len); 405 if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2)) 406 continue; 407 break; 408 } 409 410 fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1); 411 fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1); 412 fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1); 413 fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1); 414 fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum)); 415 416 setbits_8(&bcsr[15], BCSR15_QEUART_EN); 417 } 418 419 #ifdef CONFIG_FSL_ESDHC 420 421 int board_mmc_init(bd_t *bd) 422 { 423 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 424 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; 425 u8 bcsr6 = BCSR6_SD_CARD_1BIT; 426 427 if (!hwconfig("esdhc")) 428 return 0; 429 430 printf("Enabling eSDHC...\n" 431 " For eSDHC to function, I2C2 "); 432 if (esdhc_disables_uart0()) { 433 printf("and UART0 should be disabled.\n"); 434 printf(" Redirecting stderr, stdout and stdin to UART1...\n"); 435 console_assign(stderr, "eserial1"); 436 console_assign(stdout, "eserial1"); 437 console_assign(stdin, "eserial1"); 438 printf("Switched to UART1 (initial log has been printed to " 439 "UART0).\n"); 440 441 clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK, 442 PLPPAR1_ESDHC_4BITS_VAL); 443 clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK, 444 PLPDIR1_ESDHC_4BITS_VAL); 445 bcsr6 |= BCSR6_SD_CARD_4BITS; 446 } else { 447 printf("should be disabled.\n"); 448 } 449 450 /* Assign I2C2 signals to eSDHC. */ 451 clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK, 452 PLPPAR1_ESDHC_VAL); 453 clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK, 454 PLPDIR1_ESDHC_VAL); 455 456 /* Mux I2C2 (and optionally UART0) signals to eSDHC. */ 457 setbits_8(&bcsr[6], bcsr6); 458 459 return fsl_esdhc_mmc_init(bd); 460 } 461 462 static void fdt_board_fixup_esdhc(void *blob, bd_t *bd) 463 { 464 const char *status = "disabled"; 465 int off = -1; 466 467 if (!hwconfig("esdhc")) 468 return; 469 470 if (esdhc_disables_uart0()) 471 fdt_board_disable_serial(blob, bd, "serial0"); 472 473 while (1) { 474 const u32 *idx; 475 int len; 476 477 off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c"); 478 if (off < 0) 479 break; 480 481 idx = fdt_getprop(blob, off, "cell-index", &len); 482 if (!idx || len != sizeof(*idx)) 483 continue; 484 485 if (*idx == 1) { 486 fdt_setprop(blob, off, "status", status, 487 strlen(status) + 1); 488 break; 489 } 490 } 491 492 if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) { 493 off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc"); 494 if (off < 0) { 495 printf("WARNING: could not find esdhc node\n"); 496 return; 497 } 498 fdt_delprop(blob, off, "sdhci,1-bit-only"); 499 } 500 } 501 #else 502 static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {} 503 #endif 504 505 static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd) 506 { 507 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; 508 509 if (hwconfig_subarg_cmp("qe_usb", "speed", "low")) 510 clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); 511 else 512 setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); 513 514 if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) { 515 clrbits_8(&bcsr[17], BCSR17_USBVCC); 516 clrbits_8(&bcsr[17], BCSR17_USBMODE); 517 do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode", 518 "peripheral", sizeof("peripheral"), 1); 519 } else { 520 setbits_8(&bcsr[17], BCSR17_USBVCC); 521 setbits_8(&bcsr[17], BCSR17_USBMODE); 522 } 523 524 clrbits_8(&bcsr[17], BCSR17_nUSBEN); 525 } 526 527 #ifdef CONFIG_PCIE1 528 static struct pci_controller pcie1_hose; 529 #endif /* CONFIG_PCIE1 */ 530 531 #ifdef CONFIG_PCI 532 void pci_init_board(void) 533 { 534 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 535 struct fsl_pci_info pci_info[1]; 536 u32 devdisr, pordevsr, io_sel; 537 int first_free_busno = 0; 538 int num = 0; 539 540 int pcie_ep, pcie_configured; 541 542 devdisr = in_be32(&gur->devdisr); 543 pordevsr = in_be32(&gur->pordevsr); 544 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 545 546 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 547 548 #ifdef CONFIG_PCIE1 549 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 550 551 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 552 SET_STD_PCIE_INFO(pci_info[num], 1); 553 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 554 printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", 555 pcie_ep ? "Endpoint" : "Root Complex", 556 pci_info[num].regs); 557 first_free_busno = fsl_pci_init_port(&pci_info[num++], 558 &pcie1_hose, first_free_busno); 559 } else { 560 printf (" PCIE1: disabled\n"); 561 } 562 563 puts("\n"); 564 #else 565 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 566 #endif 567 568 } 569 #endif /* CONFIG_PCI */ 570 571 #if defined(CONFIG_OF_BOARD_SETUP) 572 void ft_board_setup(void *blob, bd_t *bd) 573 { 574 #if defined(CONFIG_SYS_UCC_RMII_MODE) 575 int nodeoff, off, err; 576 unsigned int val; 577 const u32 *ph; 578 const u32 *index; 579 580 /* fixup device tree for supporting rmii mode */ 581 nodeoff = -1; 582 while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff, 583 "ucc_geth")) >= 0) { 584 err = fdt_setprop_string(blob, nodeoff, "tx-clock-name", 585 "clk16"); 586 if (err < 0) { 587 printf("WARNING: could not set tx-clock-name %s.\n", 588 fdt_strerror(err)); 589 break; 590 } 591 592 err = fdt_setprop_string(blob, nodeoff, "phy-connection-type", 593 "rmii"); 594 if (err < 0) { 595 printf("WARNING: could not set phy-connection-type " 596 "%s.\n", fdt_strerror(err)); 597 break; 598 } 599 600 index = fdt_getprop(blob, nodeoff, "cell-index", 0); 601 if (index == NULL) { 602 printf("WARNING: could not get cell-index of ucc\n"); 603 break; 604 } 605 606 ph = fdt_getprop(blob, nodeoff, "phy-handle", 0); 607 if (ph == NULL) { 608 printf("WARNING: could not get phy-handle of ucc\n"); 609 break; 610 } 611 612 off = fdt_node_offset_by_phandle(blob, *ph); 613 if (off < 0) { 614 printf("WARNING: could not get phy node %s.\n", 615 fdt_strerror(err)); 616 break; 617 } 618 619 val = 0x7 + *index; /* RMII phy address starts from 0x8 */ 620 621 err = fdt_setprop(blob, off, "reg", &val, sizeof(u32)); 622 if (err < 0) { 623 printf("WARNING: could not set reg for phy-handle " 624 "%s.\n", fdt_strerror(err)); 625 break; 626 } 627 } 628 #endif 629 ft_cpu_setup(blob, bd); 630 631 #ifdef CONFIG_PCIE1 632 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 633 #endif 634 fdt_board_fixup_esdhc(blob, bd); 635 fdt_board_fixup_qe_uart(blob, bd); 636 fdt_board_fixup_qe_usb(blob, bd); 637 } 638 #endif 639