1 /*
2  * Copyright 2009-2010 Freescale Semiconductor.
3  *
4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <console.h>
11 #include <hwconfig.h>
12 #include <pci.h>
13 #include <asm/processor.h>
14 #include <asm/mmu.h>
15 #include <asm/cache.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_pci.h>
18 #include <fsl_ddr_sdram.h>
19 #include <asm/fsl_serdes.h>
20 #include <asm/io.h>
21 #include <spd_sdram.h>
22 #include <i2c.h>
23 #include <ioports.h>
24 #include <linux/libfdt.h>
25 #include <fdt_support.h>
26 #include <fsl_esdhc.h>
27 #include <phy.h>
28 
29 #include "bcsr.h"
30 #if defined(CONFIG_PQ_MDS_PIB)
31 #include "../common/pq-mds-pib.h"
32 #endif
33 
34 const qe_iop_conf_t qe_iop_conf_tab[] = {
35 	/* QE_MUX_MDC */
36 	{2,  31, 1, 0, 1}, /* QE_MUX_MDC               */
37 
38 	/* QE_MUX_MDIO */
39 	{2,  30, 3, 0, 2}, /* QE_MUX_MDIO              */
40 
41 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
42 	/* UCC_1_RGMII */
43 	{2, 11, 2, 0, 1}, /* CLK12 */
44 	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
45 	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
46 	{0,  2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2      */
47 	{0,  3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
48 	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
49 	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
50 	{0,  8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
51 	{0,  9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
52 	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
53 	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
54 	{2,  8, 2, 0, 1}, /* ENET1_GRXCLK              */
55 	{2, 20, 1, 0, 2}, /* ENET1_GTXCLK              */
56 
57 	/* UCC_2_RGMII */
58 	{2, 16, 2, 0, 3}, /* CLK17 */
59 	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
60 	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
61 	{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2      */
62 	{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3      */
63 	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
64 	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
65 	{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2      */
66 	{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3      */
67 	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
68 	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
69 	{2,  3, 2, 0, 1}, /* ENET2_GRXCLK              */
70 	{2,  2, 1, 0, 2}, /* ENET2_GTXCLK              */
71 
72 	/* UCC_3_RGMII */
73 	{2, 11, 2, 0, 1}, /* CLK12 */
74 	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
75 	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
76 	{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2      */
77 	{1,  0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3      */
78 	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
79 	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
80 	{1,  5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2      */
81 	{1,  6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3      */
82 	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
83 	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
84 	{2,  9, 2, 0, 2}, /* ENET3_GRXCLK              */
85 	{2, 25, 1, 0, 2}, /* ENET3_GTXCLK              */
86 
87 	/* UCC_4_RGMII */
88 	{2, 16, 2, 0, 3}, /* CLK17 */
89 	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
90 	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
91 	{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2      */
92 	{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3      */
93 	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
94 	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
95 	{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2      */
96 	{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3      */
97 	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
98 	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
99 	{2, 17, 2, 0, 2}, /* ENET4_GRXCLK              */
100 	{2, 24, 1, 0, 2}, /* ENET4_GTXCLK              */
101 
102 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
103 	/* UCC_1_RMII */
104 	{2, 15, 2, 0, 1}, /* CLK16 */
105 	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
106 	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
107 	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
108 	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
109 	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
110 	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
111 
112 	/* UCC_2_RMII */
113 	{2, 15, 2, 0, 1}, /* CLK16 */
114 	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
115 	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
116 	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
117 	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
118 	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
119 	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
120 
121 	/* UCC_3_RMII */
122 	{2, 15, 2, 0, 1}, /* CLK16 */
123 	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
124 	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
125 	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
126 	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
127 	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
128 	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
129 
130 	/* UCC_4_RMII */
131 	{2, 15, 2, 0, 1}, /* CLK16 */
132 	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
133 	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
134 	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
135 	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
136 	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
137 	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
138 #endif
139 
140 	/* UART1 is muxed with QE PortF bit [9-12].*/
141 	{5, 12, 2, 0, 3}, /* UART1_SIN */
142 	{5, 9,  1, 0, 3}, /* UART1_SOUT */
143 	{5, 10, 2, 0, 3}, /* UART1_CTS_B */
144 	{5, 11, 1, 0, 2}, /* UART1_RTS_B */
145 
146 	/* QE UART                                     */
147 	{0, 19, 1, 0, 2}, /* QEUART_TX                 */
148 	{1, 17, 2, 0, 3}, /* QEUART_RX                 */
149 	{0, 25, 1, 0, 1}, /* QEUART_RTS                */
150 	{1, 23, 2, 0, 1}, /* QEUART_CTS                */
151 
152 	/* QE USB                                      */
153 	{5,  3, 1, 0, 1}, /* USB_OE                    */
154 	{5,  4, 1, 0, 2}, /* USB_TP                    */
155 	{5,  5, 1, 0, 2}, /* USB_TN                    */
156 	{5,  6, 2, 0, 2}, /* USB_RP                    */
157 	{5,  7, 2, 0, 1}, /* USB_RX                    */
158 	{5,  8, 2, 0, 1}, /* USB_RN                    */
159 	{2,  4, 2, 0, 2}, /* CLK5                      */
160 
161 	/* SPI Flash, M25P40                           */
162 	{4, 27, 3, 0, 1}, /* SPI_MOSI                  */
163 	{4, 28, 3, 0, 1}, /* SPI_MISO                  */
164 	{4, 29, 3, 0, 1}, /* SPI_CLK                   */
165 	{4, 30, 1, 0, 0}, /* SPI_SEL, GPIO             */
166 
167 	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
168 };
169 
170 void local_bus_init(void);
171 
172 int board_early_init_f (void)
173 {
174 	/*
175 	 * Initialize local bus.
176 	 */
177 	local_bus_init ();
178 
179 	enable_8569mds_flash_write();
180 
181 #ifdef CONFIG_QE
182 	enable_8569mds_qe_uec();
183 #endif
184 
185 #if CONFIG_SYS_I2C2_OFFSET
186 	/* Enable I2C2 signals instead of SD signals */
187 	volatile struct ccsr_gur *gur;
188 	gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
189 	gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
190 	gur->plppar1 |= PLPPAR1_I2C2_VAL;
191 	gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
192 	gur->plpdir1 |= PLPDIR1_I2C2_VAL;
193 
194 	disable_8569mds_brd_eeprom_write_protect();
195 #endif
196 
197 	return 0;
198 }
199 
200 int board_early_init_r(void)
201 {
202 	const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
203 	const u8 flash_esel = 0;
204 
205 	/*
206 	 * Remap Boot flash to caching-inhibited
207 	 * so that flash can be erased properly.
208 	 */
209 
210 	/* Flush d-cache and invalidate i-cache of any FLASH data */
211 	flush_dcache();
212 	invalidate_icache();
213 
214 	/* invalidate existing TLB entry for flash */
215 	disable_tlb(flash_esel);
216 
217 	set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE,	/* tlb, epn, rpn */
218 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
219 		0, flash_esel,				/* ts, esel */
220 		BOOKE_PAGESZ_64M, 1);			/* tsize, iprot */
221 
222 	return 0;
223 }
224 
225 int checkboard (void)
226 {
227 	printf ("Board: 8569 MDS\n");
228 
229 	return 0;
230 }
231 
232 #if !defined(CONFIG_SPD_EEPROM)
233 phys_size_t fixed_sdram(void)
234 {
235 	struct ccsr_ddr __iomem *ddr =
236 		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
237 	uint d_init;
238 
239 	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
240 	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
241 	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
242 	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
243 	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
244 	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
245 	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
246 	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
247 	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
248 	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
249 	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
250 	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
251 	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
252 	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
253 	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
254 	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
255 	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
256 	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
257 #if defined (CONFIG_DDR_ECC)
258 	out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
259 	out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
260 	out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
261 #endif
262 	udelay(500);
263 
264 	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
265 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
266 	d_init = 1;
267 	debug("DDR - 1st controller: memory initializing\n");
268 	/*
269 	 * Poll until memory is initialized.
270 	 * 512 Meg at 400 might hit this 200 times or so.
271 	 */
272 	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
273 		udelay(1000);
274 	}
275 	debug("DDR: memory initialized\n\n");
276 	udelay(500);
277 #endif
278 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
279 }
280 #endif
281 
282 /*
283  * Initialize Local Bus
284  */
285 void
286 local_bus_init(void)
287 {
288 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
289 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
290 
291 	uint clkdiv;
292 	sys_info_t sysinfo;
293 
294 	get_sys_info(&sysinfo);
295 	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
296 
297 	out_be32(&gur->lbiuiplldcr1, 0x00078080);
298 	if (clkdiv == 16)
299 		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
300 	else if (clkdiv == 8)
301 		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
302 	else if (clkdiv == 4)
303 		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
304 
305 	out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
306 }
307 
308 static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
309 {
310 	const char *status = "disabled";
311 	int off;
312 	int err;
313 
314 	off = fdt_path_offset(blob, alias);
315 	if (off < 0) {
316 		printf("WARNING: could not find %s alias: %s.\n", alias,
317 			fdt_strerror(off));
318 		return;
319 	}
320 
321 	err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
322 	if (err) {
323 		printf("WARNING: could not set status for serial0: %s.\n",
324 			fdt_strerror(err));
325 		return;
326 	}
327 }
328 
329 /*
330  * Because of an erratum in prototype boards it is impossible to use eSDHC
331  * without disabling UART0 (which makes it quite easy to 'brick' the board
332  * by simply issung 'setenv hwconfig esdhc', and not able to interact with
333  * U-Boot anylonger).
334  *
335  * So, but default we assume that the board is a prototype, which is a most
336  * safe assumption. There is no way to determine board revision from a
337  * register, so we use hwconfig.
338  */
339 
340 static int prototype_board(void)
341 {
342 	if (hwconfig_subarg("board", "rev", NULL))
343 		return hwconfig_subarg_cmp("board", "rev", "prototype");
344 	return 1;
345 }
346 
347 static int esdhc_disables_uart0(void)
348 {
349 	return prototype_board() ||
350 	       hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
351 }
352 
353 static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
354 {
355 	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
356 	const char *devtype = "serial";
357 	const char *compat = "ucc_uart";
358 	const char *clk = "brg9";
359 	u32 portnum = 0;
360 	int off = -1;
361 
362 	if (!hwconfig("qe_uart"))
363 		return;
364 
365 	if (hwconfig("esdhc") && esdhc_disables_uart0()) {
366 		printf("QE UART: won't enable with esdhc.\n");
367 		return;
368 	}
369 
370 	fdt_board_disable_serial(blob, bd, "serial1");
371 
372 	while (1) {
373 		const u32 *idx;
374 		int len;
375 
376 		off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
377 		if (off < 0) {
378 			printf("WARNING: unable to fixup device tree for "
379 				"QE UART\n");
380 			return;
381 		}
382 
383 		idx = fdt_getprop(blob, off, "cell-index", &len);
384 		if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
385 			continue;
386 		break;
387 	}
388 
389 	fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
390 	fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
391 	fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
392 	fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
393 	fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
394 
395 	setbits_8(&bcsr[15], BCSR15_QEUART_EN);
396 }
397 
398 #ifdef CONFIG_FSL_ESDHC
399 
400 int board_mmc_init(bd_t *bd)
401 {
402 	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
403 	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
404 	u8 bcsr6 = BCSR6_SD_CARD_1BIT;
405 
406 	if (!hwconfig("esdhc"))
407 		return 0;
408 
409 	printf("Enabling eSDHC...\n"
410 	       "  For eSDHC to function, I2C2 ");
411 	if (esdhc_disables_uart0()) {
412 		printf("and UART0 should be disabled.\n");
413 		printf("  Redirecting stderr, stdout and stdin to UART1...\n");
414 		console_assign(stderr, "eserial1");
415 		console_assign(stdout, "eserial1");
416 		console_assign(stdin, "eserial1");
417 		printf("Switched to UART1 (initial log has been printed to "
418 		       "UART0).\n");
419 
420 		clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
421 					       PLPPAR1_ESDHC_4BITS_VAL);
422 		clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
423 					       PLPDIR1_ESDHC_4BITS_VAL);
424 		bcsr6 |= BCSR6_SD_CARD_4BITS;
425 	} else {
426 		printf("should be disabled.\n");
427 	}
428 
429 	/* Assign I2C2 signals to eSDHC. */
430 	clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
431 				       PLPPAR1_ESDHC_VAL);
432 	clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
433 				       PLPDIR1_ESDHC_VAL);
434 
435 	/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
436 	setbits_8(&bcsr[6], bcsr6);
437 
438 	return fsl_esdhc_mmc_init(bd);
439 }
440 
441 static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
442 {
443 	const char *status = "disabled";
444 	int off = -1;
445 
446 	if (!hwconfig("esdhc"))
447 		return;
448 
449 	if (esdhc_disables_uart0())
450 		fdt_board_disable_serial(blob, bd, "serial0");
451 
452 	while (1) {
453 		const u32 *idx;
454 		int len;
455 
456 		off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
457 		if (off < 0)
458 			break;
459 
460 		idx = fdt_getprop(blob, off, "cell-index", &len);
461 		if (!idx || len != sizeof(*idx))
462 			continue;
463 
464 		if (*idx == 1) {
465 			fdt_setprop(blob, off, "status", status,
466 				    strlen(status) + 1);
467 			break;
468 		}
469 	}
470 
471 	if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
472 		off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
473 		if (off < 0) {
474 			printf("WARNING: could not find esdhc node\n");
475 			return;
476 		}
477 		fdt_delprop(blob, off, "sdhci,1-bit-only");
478 	}
479 }
480 #else
481 static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
482 #endif
483 
484 static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
485 {
486 	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
487 
488 	if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
489 		clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
490 	else
491 		setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
492 
493 	if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
494 		clrbits_8(&bcsr[17], BCSR17_USBVCC);
495 		clrbits_8(&bcsr[17], BCSR17_USBMODE);
496 		do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
497 				   "peripheral", sizeof("peripheral"), 1);
498 	} else {
499 		setbits_8(&bcsr[17], BCSR17_USBVCC);
500 		setbits_8(&bcsr[17], BCSR17_USBMODE);
501 	}
502 
503 	clrbits_8(&bcsr[17], BCSR17_nUSBEN);
504 }
505 
506 #ifdef CONFIG_PCI
507 void pci_init_board(void)
508 {
509 #if defined(CONFIG_PQ_MDS_PIB)
510 	pib_init();
511 #endif
512 
513 	fsl_pcie_init_board(0);
514 }
515 #endif /* CONFIG_PCI */
516 
517 #if defined(CONFIG_OF_BOARD_SETUP)
518 int ft_board_setup(void *blob, bd_t *bd)
519 {
520 #if defined(CONFIG_SYS_UCC_RMII_MODE)
521 	int nodeoff, off, err;
522 	unsigned int val;
523 	const u32 *ph;
524 	const u32 *index;
525 
526 	/* fixup device tree for supporting rmii mode */
527 	nodeoff = -1;
528 	while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
529 				"ucc_geth")) >= 0) {
530 		err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
531 						"clk16");
532 		if (err < 0) {
533 			printf("WARNING: could not set tx-clock-name %s.\n",
534 				fdt_strerror(err));
535 			break;
536 		}
537 
538 		err = fdt_fixup_phy_connection(blob, nodeoff,
539 				PHY_INTERFACE_MODE_RMII);
540 
541 		if (err < 0) {
542 			printf("WARNING: could not set phy-connection-type "
543 				"%s.\n", fdt_strerror(err));
544 			break;
545 		}
546 
547 		index = fdt_getprop(blob, nodeoff, "cell-index", 0);
548 		if (index == NULL) {
549 			printf("WARNING: could not get cell-index of ucc\n");
550 			break;
551 		}
552 
553 		ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
554 		if (ph == NULL) {
555 			printf("WARNING: could not get phy-handle of ucc\n");
556 			break;
557 		}
558 
559 		off = fdt_node_offset_by_phandle(blob, *ph);
560 		if (off < 0) {
561 			printf("WARNING: could not get phy node	%s.\n",
562 				fdt_strerror(err));
563 			break;
564 		}
565 
566 		val = 0x7 + *index; /* RMII phy address starts from 0x8 */
567 
568 		err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
569 		if (err < 0) {
570 			printf("WARNING: could not set reg for phy-handle "
571 				"%s.\n", fdt_strerror(err));
572 			break;
573 		}
574 	}
575 #endif
576 	ft_cpu_setup(blob, bd);
577 
578 	FT_FSL_PCI_SETUP;
579 
580 	fdt_board_fixup_esdhc(blob, bd);
581 	fdt_board_fixup_qe_uart(blob, bd);
582 	fdt_board_fixup_qe_usb(blob, bd);
583 
584 	return 0;
585 }
586 #endif
587