1 /* 2 * Copyright 2009-2010 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <hwconfig.h> 27 #include <pci.h> 28 #include <asm/processor.h> 29 #include <asm/mmu.h> 30 #include <asm/cache.h> 31 #include <asm/immap_85xx.h> 32 #include <asm/fsl_pci.h> 33 #include <asm/fsl_ddr_sdram.h> 34 #include <asm/io.h> 35 #include <spd_sdram.h> 36 #include <i2c.h> 37 #include <ioports.h> 38 #include <libfdt.h> 39 #include <fdt_support.h> 40 #include <fsl_esdhc.h> 41 42 #include "bcsr.h" 43 #if defined(CONFIG_PQ_MDS_PIB) 44 #include "../common/pq-mds-pib.h" 45 #endif 46 47 phys_size_t fixed_sdram(void); 48 49 const qe_iop_conf_t qe_iop_conf_tab[] = { 50 /* QE_MUX_MDC */ 51 {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ 52 53 /* QE_MUX_MDIO */ 54 {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */ 55 56 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 57 /* UCC_1_RGMII */ 58 {2, 11, 2, 0, 1}, /* CLK12 */ 59 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ 60 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ 61 {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */ 62 {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ 63 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ 64 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ 65 {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ 66 {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ 67 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 68 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ 69 {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */ 70 {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */ 71 72 /* UCC_2_RGMII */ 73 {2, 16, 2, 0, 3}, /* CLK17 */ 74 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ 75 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ 76 {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */ 77 {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */ 78 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ 79 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ 80 {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */ 81 {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */ 82 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ 83 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ 84 {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */ 85 {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */ 86 87 /* UCC_3_RGMII */ 88 {2, 11, 2, 0, 1}, /* CLK12 */ 89 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ 90 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ 91 {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */ 92 {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */ 93 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ 94 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ 95 {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */ 96 {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */ 97 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ 98 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ 99 {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */ 100 {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */ 101 102 /* UCC_4_RGMII */ 103 {2, 16, 2, 0, 3}, /* CLK17 */ 104 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ 105 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ 106 {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */ 107 {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */ 108 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ 109 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ 110 {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */ 111 {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */ 112 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ 113 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ 114 {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */ 115 {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */ 116 117 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 118 /* UCC_1_RMII */ 119 {2, 15, 2, 0, 1}, /* CLK16 */ 120 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ 121 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ 122 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ 123 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ 124 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 125 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ 126 127 /* UCC_2_RMII */ 128 {2, 15, 2, 0, 1}, /* CLK16 */ 129 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ 130 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ 131 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ 132 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ 133 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ 134 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ 135 136 /* UCC_3_RMII */ 137 {2, 15, 2, 0, 1}, /* CLK16 */ 138 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ 139 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ 140 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ 141 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ 142 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ 143 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ 144 145 /* UCC_4_RMII */ 146 {2, 15, 2, 0, 1}, /* CLK16 */ 147 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ 148 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ 149 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ 150 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ 151 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ 152 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ 153 #endif 154 155 /* UART1 is muxed with QE PortF bit [9-12].*/ 156 {5, 12, 2, 0, 3}, /* UART1_SIN */ 157 {5, 9, 1, 0, 3}, /* UART1_SOUT */ 158 {5, 10, 2, 0, 3}, /* UART1_CTS_B */ 159 {5, 11, 1, 0, 2}, /* UART1_RTS_B */ 160 161 /* QE UART */ 162 {0, 19, 1, 0, 2}, /* QEUART_TX */ 163 {1, 17, 2, 0, 3}, /* QEUART_RX */ 164 {0, 25, 1, 0, 1}, /* QEUART_RTS */ 165 {1, 23, 2, 0, 1}, /* QEUART_CTS */ 166 167 /* QE USB */ 168 {5, 3, 1, 0, 1}, /* USB_OE */ 169 {5, 4, 1, 0, 2}, /* USB_TP */ 170 {5, 5, 1, 0, 2}, /* USB_TN */ 171 {5, 6, 2, 0, 2}, /* USB_RP */ 172 {5, 7, 2, 0, 1}, /* USB_RX */ 173 {5, 8, 2, 0, 1}, /* USB_RN */ 174 {2, 4, 2, 0, 2}, /* CLK5 */ 175 176 /* SPI Flash, M25P40 */ 177 {4, 27, 3, 0, 1}, /* SPI_MOSI */ 178 {4, 28, 3, 0, 1}, /* SPI_MISO */ 179 {4, 29, 3, 0, 1}, /* SPI_CLK */ 180 {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */ 181 182 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ 183 }; 184 185 void local_bus_init(void); 186 187 int board_early_init_f (void) 188 { 189 /* 190 * Initialize local bus. 191 */ 192 local_bus_init (); 193 194 enable_8569mds_flash_write(); 195 196 #ifdef CONFIG_QE 197 enable_8569mds_qe_uec(); 198 #endif 199 200 #if CONFIG_SYS_I2C2_OFFSET 201 /* Enable I2C2 signals instead of SD signals */ 202 volatile struct ccsr_gur *gur; 203 gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000); 204 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; 205 gur->plppar1 |= PLPPAR1_I2C2_VAL; 206 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK; 207 gur->plpdir1 |= PLPDIR1_I2C2_VAL; 208 209 disable_8569mds_brd_eeprom_write_protect(); 210 #endif 211 212 return 0; 213 } 214 215 int board_early_init_r(void) 216 { 217 const unsigned int flashbase = CONFIG_SYS_NAND_BASE; 218 const u8 flash_esel = 0; 219 220 /* 221 * Remap Boot flash to caching-inhibited 222 * so that flash can be erased properly. 223 */ 224 225 /* Flush d-cache and invalidate i-cache of any FLASH data */ 226 flush_dcache(); 227 invalidate_icache(); 228 229 /* invalidate existing TLB entry for flash */ 230 disable_tlb(flash_esel); 231 232 set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */ 233 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 234 0, flash_esel, /* ts, esel */ 235 BOOKE_PAGESZ_64M, 1); /* tsize, iprot */ 236 237 return 0; 238 } 239 240 int checkboard (void) 241 { 242 printf ("Board: 8569 MDS\n"); 243 244 return 0; 245 } 246 247 phys_size_t 248 initdram(int board_type) 249 { 250 long dram_size = 0; 251 252 puts("Initializing\n"); 253 254 #if defined(CONFIG_DDR_DLL) 255 /* 256 * Work around to stabilize DDR DLL MSYNC_IN. 257 * Errata DDR9 seems to have been fixed. 258 * This is now the workaround for Errata DDR11: 259 * Override DLL = 1, Course Adj = 1, Tap Select = 0 260 */ 261 volatile ccsr_gur_t *gur = 262 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 263 264 out_be32(&gur->ddrdllcr, 0x81000000); 265 udelay(200); 266 #endif 267 268 #ifdef CONFIG_SPD_EEPROM 269 dram_size = fsl_ddr_sdram(); 270 #else 271 dram_size = fixed_sdram(); 272 #endif 273 274 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 275 dram_size *= 0x100000; 276 277 puts(" DDR: "); 278 return dram_size; 279 } 280 281 #if !defined(CONFIG_SPD_EEPROM) 282 phys_size_t fixed_sdram(void) 283 { 284 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; 285 uint d_init; 286 287 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); 288 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); 289 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 290 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 291 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 292 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 293 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 294 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 295 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); 296 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); 297 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL); 298 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); 299 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); 300 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); 301 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); 302 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); 303 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); 304 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 305 #if defined (CONFIG_DDR_ECC) 306 out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN); 307 out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS); 308 out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE); 309 #endif 310 udelay(500); 311 312 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 313 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 314 d_init = 1; 315 debug("DDR - 1st controller: memory initializing\n"); 316 /* 317 * Poll until memory is initialized. 318 * 512 Meg at 400 might hit this 200 times or so. 319 */ 320 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 321 udelay(1000); 322 } 323 debug("DDR: memory initialized\n\n"); 324 udelay(500); 325 #endif 326 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 327 } 328 #endif 329 330 /* 331 * Initialize Local Bus 332 */ 333 void 334 local_bus_init(void) 335 { 336 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 337 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 338 339 uint clkdiv; 340 uint lbc_hz; 341 sys_info_t sysinfo; 342 343 get_sys_info(&sysinfo); 344 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 345 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 346 347 out_be32(&gur->lbiuiplldcr1, 0x00078080); 348 if (clkdiv == 16) 349 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); 350 else if (clkdiv == 8) 351 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); 352 else if (clkdiv == 4) 353 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); 354 355 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); 356 } 357 358 static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias) 359 { 360 const char *status = "disabled"; 361 int off; 362 int err; 363 364 off = fdt_path_offset(blob, alias); 365 if (off < 0) { 366 printf("WARNING: could not find %s alias: %s.\n", alias, 367 fdt_strerror(off)); 368 return; 369 } 370 371 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); 372 if (err) { 373 printf("WARNING: could not set status for serial0: %s.\n", 374 fdt_strerror(err)); 375 return; 376 } 377 } 378 379 /* 380 * Because of an erratum in prototype boards it is impossible to use eSDHC 381 * without disabling UART0 (which makes it quite easy to 'brick' the board 382 * by simply issung 'setenv hwconfig esdhc', and not able to interact with 383 * U-Boot anylonger). 384 * 385 * So, but default we assume that the board is a prototype, which is a most 386 * safe assumption. There is no way to determine board revision from a 387 * register, so we use hwconfig. 388 */ 389 390 static int prototype_board(void) 391 { 392 if (hwconfig_subarg("board", "rev", NULL)) 393 return hwconfig_subarg_cmp("board", "rev", "prototype"); 394 return 1; 395 } 396 397 static int esdhc_disables_uart0(void) 398 { 399 return prototype_board() || 400 hwconfig_subarg_cmp("esdhc", "mode", "4-bits"); 401 } 402 403 static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd) 404 { 405 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; 406 const char *devtype = "serial"; 407 const char *compat = "ucc_uart"; 408 const char *clk = "brg9"; 409 u32 portnum = 0; 410 int off = -1; 411 412 if (!hwconfig("qe_uart")) 413 return; 414 415 if (hwconfig("esdhc") && esdhc_disables_uart0()) { 416 printf("QE UART: won't enable with esdhc.\n"); 417 return; 418 } 419 420 fdt_board_disable_serial(blob, bd, "serial1"); 421 422 while (1) { 423 const u32 *idx; 424 int len; 425 426 off = fdt_node_offset_by_compatible(blob, off, "ucc_geth"); 427 if (off < 0) { 428 printf("WARNING: unable to fixup device tree for " 429 "QE UART\n"); 430 return; 431 } 432 433 idx = fdt_getprop(blob, off, "cell-index", &len); 434 if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2)) 435 continue; 436 break; 437 } 438 439 fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1); 440 fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1); 441 fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1); 442 fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1); 443 fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum)); 444 445 setbits_8(&bcsr[15], BCSR15_QEUART_EN); 446 } 447 448 #ifdef CONFIG_FSL_ESDHC 449 450 int board_mmc_init(bd_t *bd) 451 { 452 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 453 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; 454 u8 bcsr6 = BCSR6_SD_CARD_1BIT; 455 456 if (!hwconfig("esdhc")) 457 return 0; 458 459 printf("Enabling eSDHC...\n" 460 " For eSDHC to function, I2C2 "); 461 if (esdhc_disables_uart0()) { 462 printf("and UART0 should be disabled.\n"); 463 printf(" Redirecting stderr, stdout and stdin to UART1...\n"); 464 console_assign(stderr, "eserial1"); 465 console_assign(stdout, "eserial1"); 466 console_assign(stdin, "eserial1"); 467 printf("Switched to UART1 (initial log has been printed to " 468 "UART0).\n"); 469 470 clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK, 471 PLPPAR1_ESDHC_4BITS_VAL); 472 clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK, 473 PLPDIR1_ESDHC_4BITS_VAL); 474 bcsr6 |= BCSR6_SD_CARD_4BITS; 475 } else { 476 printf("should be disabled.\n"); 477 } 478 479 /* Assign I2C2 signals to eSDHC. */ 480 clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK, 481 PLPPAR1_ESDHC_VAL); 482 clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK, 483 PLPDIR1_ESDHC_VAL); 484 485 /* Mux I2C2 (and optionally UART0) signals to eSDHC. */ 486 setbits_8(&bcsr[6], bcsr6); 487 488 return fsl_esdhc_mmc_init(bd); 489 } 490 491 static void fdt_board_fixup_esdhc(void *blob, bd_t *bd) 492 { 493 const char *status = "disabled"; 494 int off = -1; 495 496 if (!hwconfig("esdhc")) 497 return; 498 499 if (esdhc_disables_uart0()) 500 fdt_board_disable_serial(blob, bd, "serial0"); 501 502 while (1) { 503 const u32 *idx; 504 int len; 505 506 off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c"); 507 if (off < 0) 508 break; 509 510 idx = fdt_getprop(blob, off, "cell-index", &len); 511 if (!idx || len != sizeof(*idx)) 512 continue; 513 514 if (*idx == 1) { 515 fdt_setprop(blob, off, "status", status, 516 strlen(status) + 1); 517 break; 518 } 519 } 520 521 if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) { 522 off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc"); 523 if (off < 0) { 524 printf("WARNING: could not find esdhc node\n"); 525 return; 526 } 527 fdt_delprop(blob, off, "sdhci,1-bit-only"); 528 } 529 } 530 #else 531 static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {} 532 #endif 533 534 static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd) 535 { 536 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; 537 538 if (hwconfig_subarg_cmp("qe_usb", "speed", "low")) 539 clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); 540 else 541 setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); 542 543 if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) { 544 clrbits_8(&bcsr[17], BCSR17_USBVCC); 545 clrbits_8(&bcsr[17], BCSR17_USBMODE); 546 do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode", 547 "peripheral", sizeof("peripheral"), 1); 548 } else { 549 setbits_8(&bcsr[17], BCSR17_USBVCC); 550 setbits_8(&bcsr[17], BCSR17_USBMODE); 551 } 552 553 clrbits_8(&bcsr[17], BCSR17_nUSBEN); 554 } 555 556 #ifdef CONFIG_PCIE1 557 static struct pci_controller pcie1_hose; 558 #endif /* CONFIG_PCIE1 */ 559 560 #ifdef CONFIG_PCI 561 void pci_init_board(void) 562 { 563 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 564 struct fsl_pci_info pci_info[1]; 565 u32 devdisr, pordevsr, io_sel; 566 int first_free_busno = 0; 567 int num = 0; 568 569 int pcie_ep, pcie_configured; 570 571 devdisr = in_be32(&gur->devdisr); 572 pordevsr = in_be32(&gur->pordevsr); 573 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 574 575 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 576 577 #if defined(CONFIG_PQ_MDS_PIB) 578 pib_init(); 579 #endif 580 581 #ifdef CONFIG_PCIE1 582 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 583 584 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 585 SET_STD_PCIE_INFO(pci_info[num], 1); 586 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 587 printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", 588 pcie_ep ? "Endpoint" : "Root Complex", 589 pci_info[num].regs); 590 first_free_busno = fsl_pci_init_port(&pci_info[num++], 591 &pcie1_hose, first_free_busno); 592 } else { 593 printf (" PCIE1: disabled\n"); 594 } 595 596 puts("\n"); 597 #else 598 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 599 #endif 600 601 } 602 #endif /* CONFIG_PCI */ 603 604 #if defined(CONFIG_OF_BOARD_SETUP) 605 void ft_board_setup(void *blob, bd_t *bd) 606 { 607 #if defined(CONFIG_SYS_UCC_RMII_MODE) 608 int nodeoff, off, err; 609 unsigned int val; 610 const u32 *ph; 611 const u32 *index; 612 613 /* fixup device tree for supporting rmii mode */ 614 nodeoff = -1; 615 while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff, 616 "ucc_geth")) >= 0) { 617 err = fdt_setprop_string(blob, nodeoff, "tx-clock-name", 618 "clk16"); 619 if (err < 0) { 620 printf("WARNING: could not set tx-clock-name %s.\n", 621 fdt_strerror(err)); 622 break; 623 } 624 625 err = fdt_setprop_string(blob, nodeoff, "phy-connection-type", 626 "rmii"); 627 if (err < 0) { 628 printf("WARNING: could not set phy-connection-type " 629 "%s.\n", fdt_strerror(err)); 630 break; 631 } 632 633 index = fdt_getprop(blob, nodeoff, "cell-index", 0); 634 if (index == NULL) { 635 printf("WARNING: could not get cell-index of ucc\n"); 636 break; 637 } 638 639 ph = fdt_getprop(blob, nodeoff, "phy-handle", 0); 640 if (ph == NULL) { 641 printf("WARNING: could not get phy-handle of ucc\n"); 642 break; 643 } 644 645 off = fdt_node_offset_by_phandle(blob, *ph); 646 if (off < 0) { 647 printf("WARNING: could not get phy node %s.\n", 648 fdt_strerror(err)); 649 break; 650 } 651 652 val = 0x7 + *index; /* RMII phy address starts from 0x8 */ 653 654 err = fdt_setprop(blob, off, "reg", &val, sizeof(u32)); 655 if (err < 0) { 656 printf("WARNING: could not set reg for phy-handle " 657 "%s.\n", fdt_strerror(err)); 658 break; 659 } 660 } 661 #endif 662 ft_cpu_setup(blob, bd); 663 664 FT_FSL_PCI_SETUP; 665 666 fdt_board_fixup_esdhc(blob, bd); 667 fdt_board_fixup_qe_uart(blob, bd); 668 fdt_board_fixup_qe_usb(blob, bd); 669 } 670 #endif 671