1 /* 2 * Copyright 2009-2010 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <hwconfig.h> 27 #include <pci.h> 28 #include <asm/processor.h> 29 #include <asm/mmu.h> 30 #include <asm/immap_85xx.h> 31 #include <asm/fsl_pci.h> 32 #include <asm/fsl_ddr_sdram.h> 33 #include <asm/io.h> 34 #include <spd_sdram.h> 35 #include <i2c.h> 36 #include <ioports.h> 37 #include <libfdt.h> 38 #include <fdt_support.h> 39 #include <fsl_esdhc.h> 40 41 #include "bcsr.h" 42 #if defined(CONFIG_PQ_MDS_PIB) 43 #include "../common/pq-mds-pib.h" 44 #endif 45 46 phys_size_t fixed_sdram(void); 47 48 const qe_iop_conf_t qe_iop_conf_tab[] = { 49 /* QE_MUX_MDC */ 50 {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ 51 52 /* QE_MUX_MDIO */ 53 {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */ 54 55 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 56 /* UCC_1_RGMII */ 57 {2, 11, 2, 0, 1}, /* CLK12 */ 58 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ 59 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ 60 {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */ 61 {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ 62 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ 63 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ 64 {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ 65 {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ 66 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 67 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ 68 {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */ 69 {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */ 70 71 /* UCC_2_RGMII */ 72 {2, 16, 2, 0, 3}, /* CLK17 */ 73 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ 74 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ 75 {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */ 76 {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */ 77 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ 78 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ 79 {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */ 80 {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */ 81 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ 82 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ 83 {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */ 84 {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */ 85 86 /* UCC_3_RGMII */ 87 {2, 11, 2, 0, 1}, /* CLK12 */ 88 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ 89 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ 90 {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */ 91 {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */ 92 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ 93 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ 94 {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */ 95 {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */ 96 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ 97 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ 98 {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */ 99 {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */ 100 101 /* UCC_4_RGMII */ 102 {2, 16, 2, 0, 3}, /* CLK17 */ 103 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ 104 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ 105 {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */ 106 {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */ 107 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ 108 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ 109 {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */ 110 {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */ 111 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ 112 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ 113 {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */ 114 {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */ 115 116 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 117 /* UCC_1_RMII */ 118 {2, 15, 2, 0, 1}, /* CLK16 */ 119 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ 120 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ 121 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ 122 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ 123 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 124 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ 125 126 /* UCC_2_RMII */ 127 {2, 15, 2, 0, 1}, /* CLK16 */ 128 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ 129 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ 130 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ 131 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ 132 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ 133 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ 134 135 /* UCC_3_RMII */ 136 {2, 15, 2, 0, 1}, /* CLK16 */ 137 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ 138 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ 139 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ 140 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ 141 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ 142 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ 143 144 /* UCC_4_RMII */ 145 {2, 15, 2, 0, 1}, /* CLK16 */ 146 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ 147 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ 148 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ 149 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ 150 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ 151 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ 152 #endif 153 154 /* UART1 is muxed with QE PortF bit [9-12].*/ 155 {5, 12, 2, 0, 3}, /* UART1_SIN */ 156 {5, 9, 1, 0, 3}, /* UART1_SOUT */ 157 {5, 10, 2, 0, 3}, /* UART1_CTS_B */ 158 {5, 11, 1, 0, 2}, /* UART1_RTS_B */ 159 160 /* QE UART */ 161 {0, 19, 1, 0, 2}, /* QEUART_TX */ 162 {1, 17, 2, 0, 3}, /* QEUART_RX */ 163 {0, 25, 1, 0, 1}, /* QEUART_RTS */ 164 {1, 23, 2, 0, 1}, /* QEUART_CTS */ 165 166 /* QE USB */ 167 {5, 3, 1, 0, 1}, /* USB_OE */ 168 {5, 4, 1, 0, 2}, /* USB_TP */ 169 {5, 5, 1, 0, 2}, /* USB_TN */ 170 {5, 6, 2, 0, 2}, /* USB_RP */ 171 {5, 7, 2, 0, 1}, /* USB_RX */ 172 {5, 8, 2, 0, 1}, /* USB_RN */ 173 {2, 4, 2, 0, 2}, /* CLK5 */ 174 175 /* SPI Flash, M25P40 */ 176 {4, 27, 3, 0, 1}, /* SPI_MOSI */ 177 {4, 28, 3, 0, 1}, /* SPI_MISO */ 178 {4, 29, 3, 0, 1}, /* SPI_CLK */ 179 {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */ 180 181 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ 182 }; 183 184 void local_bus_init(void); 185 186 int board_early_init_f (void) 187 { 188 /* 189 * Initialize local bus. 190 */ 191 local_bus_init (); 192 193 enable_8569mds_flash_write(); 194 195 #ifdef CONFIG_QE 196 enable_8569mds_qe_uec(); 197 #endif 198 199 #if CONFIG_SYS_I2C2_OFFSET 200 /* Enable I2C2 signals instead of SD signals */ 201 volatile struct ccsr_gur *gur; 202 gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000); 203 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; 204 gur->plppar1 |= PLPPAR1_I2C2_VAL; 205 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK; 206 gur->plpdir1 |= PLPDIR1_I2C2_VAL; 207 208 disable_8569mds_brd_eeprom_write_protect(); 209 #endif 210 211 return 0; 212 } 213 214 int checkboard (void) 215 { 216 printf ("Board: 8569 MDS\n"); 217 218 return 0; 219 } 220 221 phys_size_t 222 initdram(int board_type) 223 { 224 long dram_size = 0; 225 226 puts("Initializing\n"); 227 228 #if defined(CONFIG_DDR_DLL) 229 /* 230 * Work around to stabilize DDR DLL MSYNC_IN. 231 * Errata DDR9 seems to have been fixed. 232 * This is now the workaround for Errata DDR11: 233 * Override DLL = 1, Course Adj = 1, Tap Select = 0 234 */ 235 volatile ccsr_gur_t *gur = 236 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 237 238 out_be32(&gur->ddrdllcr, 0x81000000); 239 udelay(200); 240 #endif 241 242 #ifdef CONFIG_SPD_EEPROM 243 dram_size = fsl_ddr_sdram(); 244 #else 245 dram_size = fixed_sdram(); 246 #endif 247 248 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 249 dram_size *= 0x100000; 250 251 puts(" DDR: "); 252 return dram_size; 253 } 254 255 #if !defined(CONFIG_SPD_EEPROM) 256 phys_size_t fixed_sdram(void) 257 { 258 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; 259 uint d_init; 260 261 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); 262 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); 263 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 264 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 265 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 266 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 267 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 268 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 269 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); 270 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); 271 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL); 272 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); 273 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); 274 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); 275 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); 276 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); 277 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); 278 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 279 #if defined (CONFIG_DDR_ECC) 280 out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN); 281 out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS); 282 out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE); 283 #endif 284 udelay(500); 285 286 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 287 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 288 d_init = 1; 289 debug("DDR - 1st controller: memory initializing\n"); 290 /* 291 * Poll until memory is initialized. 292 * 512 Meg at 400 might hit this 200 times or so. 293 */ 294 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 295 udelay(1000); 296 } 297 debug("DDR: memory initialized\n\n"); 298 udelay(500); 299 #endif 300 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 301 } 302 #endif 303 304 /* 305 * Initialize Local Bus 306 */ 307 void 308 local_bus_init(void) 309 { 310 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 311 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 312 313 uint clkdiv; 314 uint lbc_hz; 315 sys_info_t sysinfo; 316 317 get_sys_info(&sysinfo); 318 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 319 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 320 321 out_be32(&gur->lbiuiplldcr1, 0x00078080); 322 if (clkdiv == 16) 323 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); 324 else if (clkdiv == 8) 325 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); 326 else if (clkdiv == 4) 327 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); 328 329 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); 330 } 331 332 static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias) 333 { 334 const char *status = "disabled"; 335 int off; 336 int err; 337 338 off = fdt_path_offset(blob, alias); 339 if (off < 0) { 340 printf("WARNING: could not find %s alias: %s.\n", alias, 341 fdt_strerror(off)); 342 return; 343 } 344 345 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); 346 if (err) { 347 printf("WARNING: could not set status for serial0: %s.\n", 348 fdt_strerror(err)); 349 return; 350 } 351 } 352 353 /* 354 * Because of an erratum in prototype boards it is impossible to use eSDHC 355 * without disabling UART0 (which makes it quite easy to 'brick' the board 356 * by simply issung 'setenv hwconfig esdhc', and not able to interact with 357 * U-Boot anylonger). 358 * 359 * So, but default we assume that the board is a prototype, which is a most 360 * safe assumption. There is no way to determine board revision from a 361 * register, so we use hwconfig. 362 */ 363 364 static int prototype_board(void) 365 { 366 if (hwconfig_subarg("board", "rev", NULL)) 367 return hwconfig_subarg_cmp("board", "rev", "prototype"); 368 return 1; 369 } 370 371 static int esdhc_disables_uart0(void) 372 { 373 return prototype_board() || 374 hwconfig_subarg_cmp("esdhc", "mode", "4-bits"); 375 } 376 377 static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd) 378 { 379 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; 380 const char *devtype = "serial"; 381 const char *compat = "ucc_uart"; 382 const char *clk = "brg9"; 383 u32 portnum = 0; 384 int off = -1; 385 386 if (!hwconfig("qe_uart")) 387 return; 388 389 if (hwconfig("esdhc") && esdhc_disables_uart0()) { 390 printf("QE UART: won't enable with esdhc.\n"); 391 return; 392 } 393 394 fdt_board_disable_serial(blob, bd, "serial1"); 395 396 while (1) { 397 const u32 *idx; 398 int len; 399 400 off = fdt_node_offset_by_compatible(blob, off, "ucc_geth"); 401 if (off < 0) { 402 printf("WARNING: unable to fixup device tree for " 403 "QE UART\n"); 404 return; 405 } 406 407 idx = fdt_getprop(blob, off, "cell-index", &len); 408 if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2)) 409 continue; 410 break; 411 } 412 413 fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1); 414 fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1); 415 fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1); 416 fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1); 417 fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum)); 418 419 setbits_8(&bcsr[15], BCSR15_QEUART_EN); 420 } 421 422 #ifdef CONFIG_FSL_ESDHC 423 424 int board_mmc_init(bd_t *bd) 425 { 426 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 427 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; 428 u8 bcsr6 = BCSR6_SD_CARD_1BIT; 429 430 if (!hwconfig("esdhc")) 431 return 0; 432 433 printf("Enabling eSDHC...\n" 434 " For eSDHC to function, I2C2 "); 435 if (esdhc_disables_uart0()) { 436 printf("and UART0 should be disabled.\n"); 437 printf(" Redirecting stderr, stdout and stdin to UART1...\n"); 438 console_assign(stderr, "eserial1"); 439 console_assign(stdout, "eserial1"); 440 console_assign(stdin, "eserial1"); 441 printf("Switched to UART1 (initial log has been printed to " 442 "UART0).\n"); 443 444 clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK, 445 PLPPAR1_ESDHC_4BITS_VAL); 446 clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK, 447 PLPDIR1_ESDHC_4BITS_VAL); 448 bcsr6 |= BCSR6_SD_CARD_4BITS; 449 } else { 450 printf("should be disabled.\n"); 451 } 452 453 /* Assign I2C2 signals to eSDHC. */ 454 clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK, 455 PLPPAR1_ESDHC_VAL); 456 clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK, 457 PLPDIR1_ESDHC_VAL); 458 459 /* Mux I2C2 (and optionally UART0) signals to eSDHC. */ 460 setbits_8(&bcsr[6], bcsr6); 461 462 return fsl_esdhc_mmc_init(bd); 463 } 464 465 static void fdt_board_fixup_esdhc(void *blob, bd_t *bd) 466 { 467 const char *status = "disabled"; 468 int off = -1; 469 470 if (!hwconfig("esdhc")) 471 return; 472 473 if (esdhc_disables_uart0()) 474 fdt_board_disable_serial(blob, bd, "serial0"); 475 476 while (1) { 477 const u32 *idx; 478 int len; 479 480 off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c"); 481 if (off < 0) 482 break; 483 484 idx = fdt_getprop(blob, off, "cell-index", &len); 485 if (!idx || len != sizeof(*idx)) 486 continue; 487 488 if (*idx == 1) { 489 fdt_setprop(blob, off, "status", status, 490 strlen(status) + 1); 491 break; 492 } 493 } 494 495 if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) { 496 off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc"); 497 if (off < 0) { 498 printf("WARNING: could not find esdhc node\n"); 499 return; 500 } 501 fdt_delprop(blob, off, "sdhci,1-bit-only"); 502 } 503 } 504 #else 505 static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {} 506 #endif 507 508 static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd) 509 { 510 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; 511 512 if (hwconfig_subarg_cmp("qe_usb", "speed", "low")) 513 clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); 514 else 515 setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); 516 517 if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) { 518 clrbits_8(&bcsr[17], BCSR17_USBVCC); 519 clrbits_8(&bcsr[17], BCSR17_USBMODE); 520 do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode", 521 "peripheral", sizeof("peripheral"), 1); 522 } else { 523 setbits_8(&bcsr[17], BCSR17_USBVCC); 524 setbits_8(&bcsr[17], BCSR17_USBMODE); 525 } 526 527 clrbits_8(&bcsr[17], BCSR17_nUSBEN); 528 } 529 530 #ifdef CONFIG_PCIE1 531 static struct pci_controller pcie1_hose; 532 #endif /* CONFIG_PCIE1 */ 533 534 #ifdef CONFIG_PCI 535 void pci_init_board(void) 536 { 537 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 538 struct fsl_pci_info pci_info[1]; 539 u32 devdisr, pordevsr, io_sel; 540 int first_free_busno = 0; 541 int num = 0; 542 543 int pcie_ep, pcie_configured; 544 545 devdisr = in_be32(&gur->devdisr); 546 pordevsr = in_be32(&gur->pordevsr); 547 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 548 549 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 550 551 #if defined(CONFIG_PQ_MDS_PIB) 552 pib_init(); 553 #endif 554 555 #ifdef CONFIG_PCIE1 556 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 557 558 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 559 SET_STD_PCIE_INFO(pci_info[num], 1); 560 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 561 printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", 562 pcie_ep ? "Endpoint" : "Root Complex", 563 pci_info[num].regs); 564 first_free_busno = fsl_pci_init_port(&pci_info[num++], 565 &pcie1_hose, first_free_busno); 566 } else { 567 printf (" PCIE1: disabled\n"); 568 } 569 570 puts("\n"); 571 #else 572 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 573 #endif 574 575 } 576 #endif /* CONFIG_PCI */ 577 578 #if defined(CONFIG_OF_BOARD_SETUP) 579 void ft_board_setup(void *blob, bd_t *bd) 580 { 581 #if defined(CONFIG_SYS_UCC_RMII_MODE) 582 int nodeoff, off, err; 583 unsigned int val; 584 const u32 *ph; 585 const u32 *index; 586 587 /* fixup device tree for supporting rmii mode */ 588 nodeoff = -1; 589 while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff, 590 "ucc_geth")) >= 0) { 591 err = fdt_setprop_string(blob, nodeoff, "tx-clock-name", 592 "clk16"); 593 if (err < 0) { 594 printf("WARNING: could not set tx-clock-name %s.\n", 595 fdt_strerror(err)); 596 break; 597 } 598 599 err = fdt_setprop_string(blob, nodeoff, "phy-connection-type", 600 "rmii"); 601 if (err < 0) { 602 printf("WARNING: could not set phy-connection-type " 603 "%s.\n", fdt_strerror(err)); 604 break; 605 } 606 607 index = fdt_getprop(blob, nodeoff, "cell-index", 0); 608 if (index == NULL) { 609 printf("WARNING: could not get cell-index of ucc\n"); 610 break; 611 } 612 613 ph = fdt_getprop(blob, nodeoff, "phy-handle", 0); 614 if (ph == NULL) { 615 printf("WARNING: could not get phy-handle of ucc\n"); 616 break; 617 } 618 619 off = fdt_node_offset_by_phandle(blob, *ph); 620 if (off < 0) { 621 printf("WARNING: could not get phy node %s.\n", 622 fdt_strerror(err)); 623 break; 624 } 625 626 val = 0x7 + *index; /* RMII phy address starts from 0x8 */ 627 628 err = fdt_setprop(blob, off, "reg", &val, sizeof(u32)); 629 if (err < 0) { 630 printf("WARNING: could not set reg for phy-handle " 631 "%s.\n", fdt_strerror(err)); 632 break; 633 } 634 } 635 #endif 636 ft_cpu_setup(blob, bd); 637 638 FT_FSL_PCI_SETUP; 639 640 fdt_board_fixup_esdhc(blob, bd); 641 fdt_board_fixup_qe_uart(blob, bd); 642 fdt_board_fixup_qe_usb(blob, bd); 643 } 644 #endif 645