1 /* 2 * Copyright 2009 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/mmu.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd_sdram.h> 34 #include <i2c.h> 35 #include <ioports.h> 36 #include <libfdt.h> 37 #include <fdt_support.h> 38 39 #include "bcsr.h" 40 41 phys_size_t fixed_sdram(void); 42 43 const qe_iop_conf_t qe_iop_conf_tab[] = { 44 /* QE_MUX_MDC */ 45 {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ 46 47 /* QE_MUX_MDIO */ 48 {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */ 49 50 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 51 /* UCC_1_RGMII */ 52 {2, 11, 2, 0, 1}, /* CLK12 */ 53 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ 54 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ 55 {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */ 56 {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ 57 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ 58 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ 59 {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ 60 {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ 61 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 62 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ 63 {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */ 64 {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */ 65 66 /* UCC_2_RGMII */ 67 {2, 16, 2, 0, 3}, /* CLK17 */ 68 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ 69 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ 70 {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */ 71 {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */ 72 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ 73 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ 74 {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */ 75 {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */ 76 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ 77 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ 78 {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */ 79 {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */ 80 81 /* UCC_3_RGMII */ 82 {2, 11, 2, 0, 1}, /* CLK12 */ 83 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ 84 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ 85 {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */ 86 {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */ 87 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ 88 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ 89 {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */ 90 {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */ 91 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ 92 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ 93 {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */ 94 {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */ 95 96 /* UCC_4_RGMII */ 97 {2, 16, 2, 0, 3}, /* CLK17 */ 98 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ 99 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ 100 {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */ 101 {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */ 102 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ 103 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ 104 {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */ 105 {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */ 106 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ 107 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ 108 {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */ 109 {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */ 110 111 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 112 /* UCC_1_RMII */ 113 {2, 15, 2, 0, 1}, /* CLK16 */ 114 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ 115 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ 116 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ 117 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ 118 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 119 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ 120 121 /* UCC_2_RMII */ 122 {2, 15, 2, 0, 1}, /* CLK16 */ 123 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ 124 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ 125 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ 126 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ 127 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ 128 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ 129 130 /* UCC_3_RMII */ 131 {2, 15, 2, 0, 1}, /* CLK16 */ 132 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ 133 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ 134 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ 135 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ 136 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ 137 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ 138 139 /* UCC_4_RMII */ 140 {2, 15, 2, 0, 1}, /* CLK16 */ 141 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ 142 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ 143 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ 144 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ 145 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ 146 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ 147 #endif 148 149 /* UART1 is muxed with QE PortF bit [9-12].*/ 150 {5, 12, 2, 0, 3}, /* UART1_SIN */ 151 {5, 9, 1, 0, 3}, /* UART1_SOUT */ 152 {5, 10, 2, 0, 3}, /* UART1_CTS_B */ 153 {5, 11, 1, 0, 2}, /* UART1_RTS_B */ 154 155 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ 156 }; 157 158 void local_bus_init(void); 159 160 int board_early_init_f (void) 161 { 162 /* 163 * Initialize local bus. 164 */ 165 local_bus_init (); 166 167 enable_8569mds_flash_write(); 168 169 #ifdef CONFIG_QE 170 enable_8569mds_qe_uec(); 171 #endif 172 173 #if CONFIG_SYS_I2C2_OFFSET 174 /* Enable I2C2 signals instead of SD signals */ 175 volatile struct ccsr_gur *gur; 176 gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000); 177 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; 178 gur->plppar1 |= PLPPAR1_I2C2_VAL; 179 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK; 180 gur->plpdir1 |= PLPDIR1_I2C2_VAL; 181 182 disable_8569mds_brd_eeprom_write_protect(); 183 #endif 184 185 return 0; 186 } 187 188 int checkboard (void) 189 { 190 printf ("Board: 8569 MDS\n"); 191 192 return 0; 193 } 194 195 phys_size_t 196 initdram(int board_type) 197 { 198 long dram_size = 0; 199 200 puts("Initializing\n"); 201 202 #if defined(CONFIG_DDR_DLL) 203 /* 204 * Work around to stabilize DDR DLL MSYNC_IN. 205 * Errata DDR9 seems to have been fixed. 206 * This is now the workaround for Errata DDR11: 207 * Override DLL = 1, Course Adj = 1, Tap Select = 0 208 */ 209 volatile ccsr_gur_t *gur = 210 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 211 212 out_be32(&gur->ddrdllcr, 0x81000000); 213 udelay(200); 214 #endif 215 216 #ifdef CONFIG_SPD_EEPROM 217 dram_size = fsl_ddr_sdram(); 218 #else 219 dram_size = fixed_sdram(); 220 #endif 221 222 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 223 dram_size *= 0x100000; 224 225 puts(" DDR: "); 226 return dram_size; 227 } 228 229 #if !defined(CONFIG_SPD_EEPROM) 230 phys_size_t fixed_sdram(void) 231 { 232 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; 233 uint d_init; 234 235 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); 236 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); 237 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 238 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 239 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 240 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 241 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 242 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 243 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); 244 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); 245 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL); 246 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); 247 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); 248 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); 249 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); 250 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); 251 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); 252 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 253 #if defined (CONFIG_DDR_ECC) 254 out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN); 255 out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS); 256 out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE); 257 #endif 258 udelay(500); 259 260 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 261 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 262 d_init = 1; 263 debug("DDR - 1st controller: memory initializing\n"); 264 /* 265 * Poll until memory is initialized. 266 * 512 Meg at 400 might hit this 200 times or so. 267 */ 268 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 269 udelay(1000); 270 } 271 debug("DDR: memory initialized\n\n"); 272 udelay(500); 273 #endif 274 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 275 } 276 #endif 277 278 /* 279 * Initialize Local Bus 280 */ 281 void 282 local_bus_init(void) 283 { 284 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 285 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 286 287 uint clkdiv; 288 uint lbc_hz; 289 sys_info_t sysinfo; 290 291 get_sys_info(&sysinfo); 292 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 293 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 294 295 out_be32(&gur->lbiuiplldcr1, 0x00078080); 296 if (clkdiv == 16) 297 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); 298 else if (clkdiv == 8) 299 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); 300 else if (clkdiv == 4) 301 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); 302 303 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); 304 } 305 306 #ifdef CONFIG_PCIE1 307 static struct pci_controller pcie1_hose; 308 #endif /* CONFIG_PCIE1 */ 309 310 int first_free_busno = 0; 311 312 #ifdef CONFIG_PCI 313 void 314 pci_init_board(void) 315 { 316 volatile ccsr_gur_t *gur; 317 uint io_sel; 318 uint host_agent; 319 320 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 321 io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 322 host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 323 324 #ifdef CONFIG_PCIE1 325 { 326 volatile ccsr_fsl_pci_t *pci; 327 struct pci_controller *hose; 328 int pcie_ep; 329 struct pci_region *r; 330 int pcie_configured; 331 332 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 333 hose = &pcie1_hose; 334 pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 335 r = hose->regions; 336 pcie_configured = io_sel >= 1; 337 338 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 339 printf ("\n PCIE connected to slot as %s (base address %x)", 340 pcie_ep ? "End Point" : "Root Complex", 341 (uint)pci); 342 343 if (pci->pme_msg_det) { 344 pci->pme_msg_det = 0xffffffff; 345 debug (" with errors. Clearing. Now 0x%08x", 346 pci->pme_msg_det); 347 } 348 printf ("\n"); 349 350 /* inbound */ 351 r += fsl_pci_setup_inbound_windows(r); 352 353 /* outbound memory */ 354 pci_set_region(r++, 355 CONFIG_SYS_PCIE1_MEM_BUS, 356 CONFIG_SYS_PCIE1_MEM_PHYS, 357 CONFIG_SYS_PCIE1_MEM_SIZE, 358 PCI_REGION_MEM); 359 360 /* outbound io */ 361 pci_set_region(r++, 362 CONFIG_SYS_PCIE1_IO_BUS, 363 CONFIG_SYS_PCIE1_IO_PHYS, 364 CONFIG_SYS_PCIE1_IO_SIZE, 365 PCI_REGION_IO); 366 367 hose->region_count = r - hose->regions; 368 369 hose->first_busno=first_free_busno; 370 pci_setup_indirect(hose, (int) &pci->cfg_addr, 371 (int) &pci->cfg_data); 372 373 fsl_pci_init(hose); 374 printf ("PCIE on bus %02x - %02x\n", 375 hose->first_busno,hose->last_busno); 376 377 first_free_busno=hose->last_busno+1; 378 379 } else { 380 printf (" PCIE: disabled\n"); 381 } 382 } 383 #else 384 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 385 #endif 386 } 387 #endif /* CONFIG_PCI */ 388 389 #if defined(CONFIG_OF_BOARD_SETUP) 390 void ft_board_setup(void *blob, bd_t *bd) 391 { 392 #if defined(CONFIG_SYS_UCC_RMII_MODE) 393 int nodeoff, off, err; 394 unsigned int val; 395 const u32 *ph; 396 const u32 *index; 397 398 /* fixup device tree for supporting rmii mode */ 399 nodeoff = -1; 400 while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff, 401 "ucc_geth")) >= 0) { 402 err = fdt_setprop_string(blob, nodeoff, "tx-clock-name", 403 "clk16"); 404 if (err < 0) { 405 printf("WARNING: could not set tx-clock-name %s.\n", 406 fdt_strerror(err)); 407 break; 408 } 409 410 err = fdt_setprop_string(blob, nodeoff, "phy-connection-type", 411 "rmii"); 412 if (err < 0) { 413 printf("WARNING: could not set phy-connection-type " 414 "%s.\n", fdt_strerror(err)); 415 break; 416 } 417 418 index = fdt_getprop(blob, nodeoff, "cell-index", 0); 419 if (index == NULL) { 420 printf("WARNING: could not get cell-index of ucc\n"); 421 break; 422 } 423 424 ph = fdt_getprop(blob, nodeoff, "phy-handle", 0); 425 if (ph == NULL) { 426 printf("WARNING: could not get phy-handle of ucc\n"); 427 break; 428 } 429 430 off = fdt_node_offset_by_phandle(blob, *ph); 431 if (off < 0) { 432 printf("WARNING: could not get phy node %s.\n", 433 fdt_strerror(err)); 434 break; 435 } 436 437 val = 0x7 + *index; /* RMII phy address starts from 0x8 */ 438 439 err = fdt_setprop(blob, off, "reg", &val, sizeof(u32)); 440 if (err < 0) { 441 printf("WARNING: could not set reg for phy-handle " 442 "%s.\n", fdt_strerror(err)); 443 break; 444 } 445 } 446 #endif 447 ft_cpu_setup(blob, bd); 448 449 #ifdef CONFIG_PCIE1 450 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 451 #endif 452 } 453 #endif 454