1 /*
2  * Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0
5  */
6 
7 #include <common.h>
8 
9 #include <fsl_ddr_sdram.h>
10 #include <fsl_ddr_dimm_params.h>
11 
12 void fsl_ddr_board_options(memctl_options_t *popts,
13 				dimm_params_t *pdimm,
14 				unsigned int ctrl_num)
15 {
16 	/*
17 	 * Factors to consider for clock adjust:
18 	 *	- number of chips on bus
19 	 *	- position of slot
20 	 *	- DDR1 vs. DDR2?
21 	 *	- ???
22 	 *
23 	 * This needs to be determined on a board-by-board basis.
24 	 *	0110	3/4 cycle late
25 	 *	0111	7/8 cycle late
26 	 */
27 	popts->clk_adjust = 4;
28 
29 	/*
30 	 * Factors to consider for CPO:
31 	 *	- frequency
32 	 *	- ddr1 vs. ddr2
33 	 */
34 	popts->cpo_override = 0xff;
35 
36 	/*
37 	 * Factors to consider for write data delay:
38 	 *	- number of DIMMs
39 	 *
40 	 * 1 = 1/4 clock delay
41 	 * 2 = 1/2 clock delay
42 	 * 3 = 3/4 clock delay
43 	 * 4 = 1   clock delay
44 	 * 5 = 5/4 clock delay
45 	 * 6 = 3/2 clock delay
46 	 */
47 	popts->write_data_delay = 2;
48 
49 	/*
50 	 * Enable half drive strength
51 	 */
52 	popts->half_strength_driver_enable = 1;
53 
54 	/* Write leveling override */
55 	popts->wrlvl_en = 1;
56 	popts->wrlvl_override = 1;
57 	popts->wrlvl_sample = 0xa;
58 	popts->wrlvl_start = 0x4;
59 
60 	/* Rtt and Rtt_W override */
61 	popts->rtt_override = 1;
62 	popts->rtt_override_value = DDR3_RTT_60_OHM;
63 	popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
64 }
65