xref: /openbmc/u-boot/board/freescale/mpc8569mds/ddr.c (revision 284170309cab2006e7730c65454458680921b16a)
1 /*
2  * Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8 
9 #include <common.h>
10 #include <i2c.h>
11 
12 #include <asm/fsl_ddr_sdram.h>
13 #include <asm/fsl_ddr_dimm_params.h>
14 
15 static void
16 get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
17 {
18 	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
19 }
20 
21 
22 unsigned int fsl_ddr_get_mem_data_rate(void)
23 {
24 	return get_ddr_freq(0);
25 }
26 
27 void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
28 		      unsigned int ctrl_num)
29 {
30 	unsigned int i;
31 	unsigned int i2c_address = 0;
32 
33 	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
34 		if (ctrl_num == 0 && i == 0)
35 			i2c_address = SPD_EEPROM_ADDRESS1;
36 		if (ctrl_num == 0 && i == 1)
37 			i2c_address = SPD_EEPROM_ADDRESS2;
38 		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
39 	}
40 }
41 
42 void fsl_ddr_board_options(memctl_options_t *popts,
43 				dimm_params_t *pdimm,
44 				unsigned int ctrl_num)
45 {
46 	/*
47 	 * Factors to consider for clock adjust:
48 	 *	- number of chips on bus
49 	 *	- position of slot
50 	 *	- DDR1 vs. DDR2?
51 	 *	- ???
52 	 *
53 	 * This needs to be determined on a board-by-board basis.
54 	 *	0110	3/4 cycle late
55 	 *	0111	7/8 cycle late
56 	 */
57 	popts->clk_adjust = 4;
58 
59 	/*
60 	 * Factors to consider for CPO:
61 	 *	- frequency
62 	 *	- ddr1 vs. ddr2
63 	 */
64 	popts->cpo_override = 0xff;
65 
66 	/*
67 	 * Factors to consider for write data delay:
68 	 *	- number of DIMMs
69 	 *
70 	 * 1 = 1/4 clock delay
71 	 * 2 = 1/2 clock delay
72 	 * 3 = 3/4 clock delay
73 	 * 4 = 1   clock delay
74 	 * 5 = 5/4 clock delay
75 	 * 6 = 3/2 clock delay
76 	 */
77 	popts->write_data_delay = 2;
78 
79 	/*
80 	 * Enable half drive strength
81 	 */
82 	popts->half_strength_driver_enable = 1;
83 
84 	/* Write leveling override */
85 	popts->wrlvl_en = 1;
86 	popts->wrlvl_override = 1;
87 	popts->wrlvl_sample = 0xa;
88 	popts->wrlvl_start = 0x4;
89 
90 	/* Rtt and Rtt_W override */
91 	popts->rtt_override = 1;
92 	popts->rtt_override_value = DDR3_RTT_60_OHM;
93 	popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
94 }
95