1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2008 Freescale Semiconductor, Inc. 4 * 5 * (C) Copyright 2000 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 */ 8 9 #include <common.h> 10 #include <asm/mmu.h> 11 12 struct fsl_e_tlb_entry tlb_table[] = { 13 /* TLB 0 - for temp stack in cache */ 14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 15 MAS3_SX|MAS3_SW|MAS3_SR, 0, 16 0, 0, BOOKE_PAGESZ_4K, 0), 17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 18 MAS3_SX|MAS3_SW|MAS3_SR, 0, 19 0, 0, BOOKE_PAGESZ_4K, 0), 20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21 MAS3_SX|MAS3_SW|MAS3_SR, 0, 22 0, 0, BOOKE_PAGESZ_4K, 0), 23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 24 MAS3_SX|MAS3_SW|MAS3_SR, 0, 25 0, 0, BOOKE_PAGESZ_4K, 0), 26 27 /* TLB 1 Initializations */ 28 /* 29 * TLBe 0: 16M Non-cacheable, guarded 30 * 0xff000000 16M FLASH (upper half) 31 * Out of reset this entry is only 4K. 32 */ 33 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000, 34 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 35 0, 0, BOOKE_PAGESZ_16M, 1), 36 37 /* 38 * TLBe 1: 16M Non-cacheable, guarded 39 * 0xfe000000 16M FLASH (lower half) 40 */ 41 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, 42 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 43 0, 1, BOOKE_PAGESZ_16M, 1), 44 45 /* 46 * TLBe 2: 1G Non-cacheable, guarded 47 * 0x80000000 512M PCI1 MEM 48 * 0xa0000000 512M PCIe MEM 49 */ 50 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, 51 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 52 0, 2, BOOKE_PAGESZ_1G, 1), 53 54 /* 55 * TLBe 3: 64M Non-cacheable, guarded 56 * 0xe000_0000 1M CCSRBAR 57 * 0xe200_0000 8M PCI1 IO 58 * 0xe280_0000 8M PCIe IO 59 */ 60 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 61 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 62 0, 3, BOOKE_PAGESZ_64M, 1), 63 64 /* 65 * TLBe 4: 64M Cacheable, non-guarded 66 * 0xf000_0000 64M LBC SDRAM 67 */ 68 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, 69 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 70 0, 4, BOOKE_PAGESZ_64M, 1), 71 72 /* 73 * TLBe 5: 256K Non-cacheable, guarded 74 * 0xf8000000 32K BCSR 75 * 0xf8008000 32K PIB (CS4) 76 * 0xf8010000 32K PIB (CS5) 77 */ 78 SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE, 79 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 80 0, 5, BOOKE_PAGESZ_256K, 1), 81 }; 82 83 int num_tlb_entries = ARRAY_SIZE(tlb_table); 84