1 /*
2  * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
3  *
4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #include <common.h>
26 #include <pci.h>
27 #include <asm/processor.h>
28 #include <asm/mmu.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <asm/fsl_serdes.h>
33 #include <spd_sdram.h>
34 #include <i2c.h>
35 #include <ioports.h>
36 #include <libfdt.h>
37 #include <fdt_support.h>
38 
39 #include "bcsr.h"
40 
41 const qe_iop_conf_t qe_iop_conf_tab[] = {
42 	/* GETH1 */
43 	{4, 10, 1, 0, 2}, /* TxD0 */
44 	{4,  9, 1, 0, 2}, /* TxD1 */
45 	{4,  8, 1, 0, 2}, /* TxD2 */
46 	{4,  7, 1, 0, 2}, /* TxD3 */
47 	{4, 23, 1, 0, 2}, /* TxD4 */
48 	{4, 22, 1, 0, 2}, /* TxD5 */
49 	{4, 21, 1, 0, 2}, /* TxD6 */
50 	{4, 20, 1, 0, 2}, /* TxD7 */
51 	{4, 15, 2, 0, 2}, /* RxD0 */
52 	{4, 14, 2, 0, 2}, /* RxD1 */
53 	{4, 13, 2, 0, 2}, /* RxD2 */
54 	{4, 12, 2, 0, 2}, /* RxD3 */
55 	{4, 29, 2, 0, 2}, /* RxD4 */
56 	{4, 28, 2, 0, 2}, /* RxD5 */
57 	{4, 27, 2, 0, 2}, /* RxD6 */
58 	{4, 26, 2, 0, 2}, /* RxD7 */
59 	{4, 11, 1, 0, 2}, /* TX_EN */
60 	{4, 24, 1, 0, 2}, /* TX_ER */
61 	{4, 16, 2, 0, 2}, /* RX_DV */
62 	{4, 30, 2, 0, 2}, /* RX_ER */
63 	{4, 17, 2, 0, 2}, /* RX_CLK */
64 	{4, 19, 1, 0, 2}, /* GTX_CLK */
65 	{1, 31, 2, 0, 3}, /* GTX125 */
66 
67 	/* GETH2 */
68 	{5, 10, 1, 0, 2}, /* TxD0 */
69 	{5,  9, 1, 0, 2}, /* TxD1 */
70 	{5,  8, 1, 0, 2}, /* TxD2 */
71 	{5,  7, 1, 0, 2}, /* TxD3 */
72 	{5, 23, 1, 0, 2}, /* TxD4 */
73 	{5, 22, 1, 0, 2}, /* TxD5 */
74 	{5, 21, 1, 0, 2}, /* TxD6 */
75 	{5, 20, 1, 0, 2}, /* TxD7 */
76 	{5, 15, 2, 0, 2}, /* RxD0 */
77 	{5, 14, 2, 0, 2}, /* RxD1 */
78 	{5, 13, 2, 0, 2}, /* RxD2 */
79 	{5, 12, 2, 0, 2}, /* RxD3 */
80 	{5, 29, 2, 0, 2}, /* RxD4 */
81 	{5, 28, 2, 0, 2}, /* RxD5 */
82 	{5, 27, 2, 0, 3}, /* RxD6 */
83 	{5, 26, 2, 0, 2}, /* RxD7 */
84 	{5, 11, 1, 0, 2}, /* TX_EN */
85 	{5, 24, 1, 0, 2}, /* TX_ER */
86 	{5, 16, 2, 0, 2}, /* RX_DV */
87 	{5, 30, 2, 0, 2}, /* RX_ER */
88 	{5, 17, 2, 0, 2}, /* RX_CLK */
89 	{5, 19, 1, 0, 2}, /* GTX_CLK */
90 	{1, 31, 2, 0, 3}, /* GTX125 */
91 	{4,  6, 3, 0, 2}, /* MDIO */
92 	{4,  5, 1, 0, 2}, /* MDC */
93 
94 	/* UART1 */
95 	{2, 0, 1, 0, 2}, /* UART_SOUT1 */
96 	{2, 1, 1, 0, 2}, /* UART_RTS1 */
97 	{2, 2, 2, 0, 2}, /* UART_CTS1 */
98 	{2, 3, 2, 0, 2}, /* UART_SIN1 */
99 
100 	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
101 };
102 
103 void local_bus_init(void);
104 
105 int board_early_init_f (void)
106 {
107 	/*
108 	 * Initialize local bus.
109 	 */
110 	local_bus_init ();
111 
112 	enable_8568mds_duart();
113 	enable_8568mds_flash_write();
114 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
115 	reset_8568mds_uccs();
116 #endif
117 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
118 	enable_8568mds_qe_mdio();
119 #endif
120 
121 #ifdef CONFIG_SYS_I2C2_OFFSET
122 	/* Enable I2C2_SCL and I2C2_SDA */
123 	volatile struct par_io *port_c;
124 	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
125 	port_c->cpdir2 |= 0x0f000000;
126 	port_c->cppar2 &= ~0x0f000000;
127 	port_c->cppar2 |= 0x0a000000;
128 #endif
129 
130 	return 0;
131 }
132 
133 int checkboard (void)
134 {
135 	printf ("Board: 8568 MDS\n");
136 
137 	return 0;
138 }
139 
140 /*
141  * Initialize Local Bus
142  */
143 void
144 local_bus_init(void)
145 {
146 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
147 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
148 
149 	uint clkdiv;
150 	uint lbc_hz;
151 	sys_info_t sysinfo;
152 
153 	get_sys_info(&sysinfo);
154 	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
155 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
156 
157 	gur->lbiuiplldcr1 = 0x00078080;
158 	if (clkdiv == 16) {
159 		gur->lbiuiplldcr0 = 0x7c0f1bf0;
160 	} else if (clkdiv == 8) {
161 		gur->lbiuiplldcr0 = 0x6c0f1bf0;
162 	} else if (clkdiv == 4) {
163 		gur->lbiuiplldcr0 = 0x5c0f1bf0;
164 	}
165 
166 	lbc->lcrr |= 0x00030000;
167 
168 	asm("sync;isync;msync");
169 }
170 
171 /*
172  * Initialize SDRAM memory on the Local Bus.
173  */
174 void lbc_sdram_init(void)
175 {
176 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
177 
178 	uint idx;
179 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
180 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
181 	uint lsdmr_common;
182 
183 	puts("LBC SDRAM: ");
184 	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
185 		   "\n       ");
186 
187 	/*
188 	 * Setup SDRAM Base and Option Registers
189 	 */
190 	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
191 	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
192 	asm("msync");
193 
194 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
195 	asm("msync");
196 
197 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
198 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
199 	asm("msync");
200 
201 	/*
202 	 * MPC8568 uses "new" 15-16 style addressing.
203 	 */
204 	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
205 	lsdmr_common |= LSDMR_BSMA1516;
206 
207 	/*
208 	 * Issue PRECHARGE ALL command.
209 	 */
210 	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
211 	asm("sync;msync");
212 	*sdram_addr = 0xff;
213 	ppcDcbf((unsigned long) sdram_addr);
214 	udelay(100);
215 
216 	/*
217 	 * Issue 8 AUTO REFRESH commands.
218 	 */
219 	for (idx = 0; idx < 8; idx++) {
220 		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
221 		asm("sync;msync");
222 		*sdram_addr = 0xff;
223 		ppcDcbf((unsigned long) sdram_addr);
224 		udelay(100);
225 	}
226 
227 	/*
228 	 * Issue 8 MODE-set command.
229 	 */
230 	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
231 	asm("sync;msync");
232 	*sdram_addr = 0xff;
233 	ppcDcbf((unsigned long) sdram_addr);
234 	udelay(100);
235 
236 	/*
237 	 * Issue NORMAL OP command.
238 	 */
239 	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
240 	asm("sync;msync");
241 	*sdram_addr = 0xff;
242 	ppcDcbf((unsigned long) sdram_addr);
243 	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
244 
245 #endif	/* enable SDRAM init */
246 }
247 
248 #if defined(CONFIG_PCI)
249 #ifndef CONFIG_PCI_PNP
250 static struct pci_config_table pci_mpc8568mds_config_table[] = {
251 	{
252 	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
253 	 pci_cfgfunc_config_device,
254 	 {PCI_ENET0_IOADDR,
255 	  PCI_ENET0_MEMADDR,
256 	  PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
257 	 },
258 	{}
259 };
260 #endif
261 
262 static struct pci_controller pci1_hose = {
263 #ifndef CONFIG_PCI_PNP
264 	config_table: pci_mpc8568mds_config_table,
265 #endif
266 };
267 #endif	/* CONFIG_PCI */
268 
269 /*
270  * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
271  */
272 void
273 pib_init(void)
274 {
275 	u8 val8, orig_i2c_bus;
276 	/*
277 	 * Assign PIB PMC2/3 to PCI bus
278 	 */
279 
280 	/*switch temporarily to I2C bus #2 */
281 	orig_i2c_bus = i2c_get_bus_num();
282 	i2c_set_bus_num(1);
283 
284 	val8 = 0x00;
285 	i2c_write(0x23, 0x6, 1, &val8, 1);
286 	i2c_write(0x23, 0x7, 1, &val8, 1);
287 	val8 = 0xff;
288 	i2c_write(0x23, 0x2, 1, &val8, 1);
289 	i2c_write(0x23, 0x3, 1, &val8, 1);
290 
291 	val8 = 0x00;
292 	i2c_write(0x26, 0x6, 1, &val8, 1);
293 	val8 = 0x34;
294 	i2c_write(0x26, 0x7, 1, &val8, 1);
295 	val8 = 0xf9;
296 	i2c_write(0x26, 0x2, 1, &val8, 1);
297 	val8 = 0xff;
298 	i2c_write(0x26, 0x3, 1, &val8, 1);
299 
300 	val8 = 0x00;
301 	i2c_write(0x27, 0x6, 1, &val8, 1);
302 	i2c_write(0x27, 0x7, 1, &val8, 1);
303 	val8 = 0xff;
304 	i2c_write(0x27, 0x2, 1, &val8, 1);
305 	val8 = 0xef;
306 	i2c_write(0x27, 0x3, 1, &val8, 1);
307 
308 	asm("eieio");
309 }
310 
311 #ifdef CONFIG_PCI
312 void pci_init_board(void)
313 {
314 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
315 	int first_free_busno = 0;
316 #ifdef CONFIG_PCI1
317 	struct fsl_pci_info pci_info;
318 	u32 devdisr, pordevsr, io_sel;
319 	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
320 
321 	devdisr = in_be32(&gur->devdisr);
322 	pordevsr = in_be32(&gur->pordevsr);
323 	porpllsr = in_be32(&gur->porpllsr);
324 	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
325 
326 	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
327 
328 	pci_speed = 66666000;
329 	pci_32 = 1;
330 	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
331 	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
332 
333 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
334 		SET_STD_PCI_INFO(pci_info, 1);
335 		set_next_law(pci_info.mem_phys,
336 			law_size_bits(pci_info.mem_size), pci_info.law);
337 		set_next_law(pci_info.io_phys,
338 			law_size_bits(pci_info.io_size), pci_info.law);
339 
340 		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
341 		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
342 			(pci_32) ? 32 : 64,
343 			(pci_speed == 33333000) ? "33" :
344 			(pci_speed == 66666000) ? "66" : "unknown",
345 			pci_clk_sel ? "sync" : "async",
346 			pci_agent ? "agent" : "host",
347 			pci_arb ? "arbiter" : "external-arbiter",
348 			pci_info.regs);
349 
350 		first_free_busno = fsl_pci_init_port(&pci_info,
351 					&pci1_hose, first_free_busno);
352 	} else {
353 		printf("PCI: disabled\n");
354 	}
355 
356 	puts("\n");
357 #else
358 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
359 #endif
360 
361 	fsl_pcie_init_board(first_free_busno);
362 }
363 #endif /* CONFIG_PCI */
364 
365 #if defined(CONFIG_OF_BOARD_SETUP)
366 void ft_board_setup(void *blob, bd_t *bd)
367 {
368 	ft_cpu_setup(blob, bd);
369 
370 	FT_FSL_PCI_SETUP;
371 }
372 #endif
373