1 /* 2 * Copyright 2007 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/mmu.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/immap_fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <spd_sdram.h> 33 #include <i2c.h> 34 #include <ioports.h> 35 #include <libfdt.h> 36 #include <fdt_support.h> 37 38 #include "bcsr.h" 39 40 const qe_iop_conf_t qe_iop_conf_tab[] = { 41 /* GETH1 */ 42 {4, 10, 1, 0, 2}, /* TxD0 */ 43 {4, 9, 1, 0, 2}, /* TxD1 */ 44 {4, 8, 1, 0, 2}, /* TxD2 */ 45 {4, 7, 1, 0, 2}, /* TxD3 */ 46 {4, 23, 1, 0, 2}, /* TxD4 */ 47 {4, 22, 1, 0, 2}, /* TxD5 */ 48 {4, 21, 1, 0, 2}, /* TxD6 */ 49 {4, 20, 1, 0, 2}, /* TxD7 */ 50 {4, 15, 2, 0, 2}, /* RxD0 */ 51 {4, 14, 2, 0, 2}, /* RxD1 */ 52 {4, 13, 2, 0, 2}, /* RxD2 */ 53 {4, 12, 2, 0, 2}, /* RxD3 */ 54 {4, 29, 2, 0, 2}, /* RxD4 */ 55 {4, 28, 2, 0, 2}, /* RxD5 */ 56 {4, 27, 2, 0, 2}, /* RxD6 */ 57 {4, 26, 2, 0, 2}, /* RxD7 */ 58 {4, 11, 1, 0, 2}, /* TX_EN */ 59 {4, 24, 1, 0, 2}, /* TX_ER */ 60 {4, 16, 2, 0, 2}, /* RX_DV */ 61 {4, 30, 2, 0, 2}, /* RX_ER */ 62 {4, 17, 2, 0, 2}, /* RX_CLK */ 63 {4, 19, 1, 0, 2}, /* GTX_CLK */ 64 {1, 31, 2, 0, 3}, /* GTX125 */ 65 66 /* GETH2 */ 67 {5, 10, 1, 0, 2}, /* TxD0 */ 68 {5, 9, 1, 0, 2}, /* TxD1 */ 69 {5, 8, 1, 0, 2}, /* TxD2 */ 70 {5, 7, 1, 0, 2}, /* TxD3 */ 71 {5, 23, 1, 0, 2}, /* TxD4 */ 72 {5, 22, 1, 0, 2}, /* TxD5 */ 73 {5, 21, 1, 0, 2}, /* TxD6 */ 74 {5, 20, 1, 0, 2}, /* TxD7 */ 75 {5, 15, 2, 0, 2}, /* RxD0 */ 76 {5, 14, 2, 0, 2}, /* RxD1 */ 77 {5, 13, 2, 0, 2}, /* RxD2 */ 78 {5, 12, 2, 0, 2}, /* RxD3 */ 79 {5, 29, 2, 0, 2}, /* RxD4 */ 80 {5, 28, 2, 0, 2}, /* RxD5 */ 81 {5, 27, 2, 0, 3}, /* RxD6 */ 82 {5, 26, 2, 0, 2}, /* RxD7 */ 83 {5, 11, 1, 0, 2}, /* TX_EN */ 84 {5, 24, 1, 0, 2}, /* TX_ER */ 85 {5, 16, 2, 0, 2}, /* RX_DV */ 86 {5, 30, 2, 0, 2}, /* RX_ER */ 87 {5, 17, 2, 0, 2}, /* RX_CLK */ 88 {5, 19, 1, 0, 2}, /* GTX_CLK */ 89 {1, 31, 2, 0, 3}, /* GTX125 */ 90 {4, 6, 3, 0, 2}, /* MDIO */ 91 {4, 5, 1, 0, 2}, /* MDC */ 92 93 /* UART1 */ 94 {2, 0, 1, 0, 2}, /* UART_SOUT1 */ 95 {2, 1, 1, 0, 2}, /* UART_RTS1 */ 96 {2, 2, 2, 0, 2}, /* UART_CTS1 */ 97 {2, 3, 2, 0, 2}, /* UART_SIN1 */ 98 99 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 100 }; 101 102 103 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 104 extern void ddr_enable_ecc(unsigned int dram_size); 105 #endif 106 107 void local_bus_init(void); 108 void sdram_init(void); 109 110 int board_early_init_f (void) 111 { 112 /* 113 * Initialize local bus. 114 */ 115 local_bus_init (); 116 117 enable_8568mds_duart(); 118 enable_8568mds_flash_write(); 119 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 120 reset_8568mds_uccs(); 121 #endif 122 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) 123 enable_8568mds_qe_mdio(); 124 #endif 125 126 #ifdef CONFIG_SYS_I2C2_OFFSET 127 /* Enable I2C2_SCL and I2C2_SDA */ 128 volatile struct par_io *port_c; 129 port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140); 130 port_c->cpdir2 |= 0x0f000000; 131 port_c->cppar2 &= ~0x0f000000; 132 port_c->cppar2 |= 0x0a000000; 133 #endif 134 135 return 0; 136 } 137 138 int checkboard (void) 139 { 140 printf ("Board: 8568 MDS\n"); 141 142 return 0; 143 } 144 145 phys_size_t 146 initdram(int board_type) 147 { 148 long dram_size = 0; 149 150 puts("Initializing\n"); 151 152 #if defined(CONFIG_DDR_DLL) 153 { 154 /* 155 * Work around to stabilize DDR DLL MSYNC_IN. 156 * Errata DDR9 seems to have been fixed. 157 * This is now the workaround for Errata DDR11: 158 * Override DLL = 1, Course Adj = 1, Tap Select = 0 159 */ 160 161 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 162 163 gur->ddrdllcr = 0x81000000; 164 asm("sync;isync;msync"); 165 udelay(200); 166 } 167 #endif 168 169 dram_size = fsl_ddr_sdram(); 170 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 171 dram_size *= 0x100000; 172 173 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 174 /* 175 * Initialize and enable DDR ECC. 176 */ 177 ddr_enable_ecc(dram_size); 178 #endif 179 180 /* 181 * SDRAM Initialization 182 */ 183 sdram_init(); 184 185 puts(" DDR: "); 186 return dram_size; 187 } 188 189 /* 190 * Initialize Local Bus 191 */ 192 void 193 local_bus_init(void) 194 { 195 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 196 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 197 198 uint clkdiv; 199 uint lbc_hz; 200 sys_info_t sysinfo; 201 202 get_sys_info(&sysinfo); 203 clkdiv = (lbc->lcrr & 0x0f) * 2; 204 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 205 206 gur->lbiuiplldcr1 = 0x00078080; 207 if (clkdiv == 16) { 208 gur->lbiuiplldcr0 = 0x7c0f1bf0; 209 } else if (clkdiv == 8) { 210 gur->lbiuiplldcr0 = 0x6c0f1bf0; 211 } else if (clkdiv == 4) { 212 gur->lbiuiplldcr0 = 0x5c0f1bf0; 213 } 214 215 lbc->lcrr |= 0x00030000; 216 217 asm("sync;isync;msync"); 218 } 219 220 /* 221 * Initialize SDRAM memory on the Local Bus. 222 */ 223 void 224 sdram_init(void) 225 { 226 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 227 228 uint idx; 229 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 230 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 231 uint lsdmr_common; 232 233 puts(" SDRAM: "); 234 235 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 236 237 /* 238 * Setup SDRAM Base and Option Registers 239 */ 240 lbc->or2 = CONFIG_SYS_OR2_PRELIM; 241 asm("msync"); 242 243 lbc->br2 = CONFIG_SYS_BR2_PRELIM; 244 asm("msync"); 245 246 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 247 asm("msync"); 248 249 250 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 251 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 252 asm("msync"); 253 254 /* 255 * MPC8568 uses "new" 15-16 style addressing. 256 */ 257 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 258 lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; 259 260 /* 261 * Issue PRECHARGE ALL command. 262 */ 263 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; 264 asm("sync;msync"); 265 *sdram_addr = 0xff; 266 ppcDcbf((unsigned long) sdram_addr); 267 udelay(100); 268 269 /* 270 * Issue 8 AUTO REFRESH commands. 271 */ 272 for (idx = 0; idx < 8; idx++) { 273 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; 274 asm("sync;msync"); 275 *sdram_addr = 0xff; 276 ppcDcbf((unsigned long) sdram_addr); 277 udelay(100); 278 } 279 280 /* 281 * Issue 8 MODE-set command. 282 */ 283 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; 284 asm("sync;msync"); 285 *sdram_addr = 0xff; 286 ppcDcbf((unsigned long) sdram_addr); 287 udelay(100); 288 289 /* 290 * Issue NORMAL OP command. 291 */ 292 lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; 293 asm("sync;msync"); 294 *sdram_addr = 0xff; 295 ppcDcbf((unsigned long) sdram_addr); 296 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 297 298 #endif /* enable SDRAM init */ 299 } 300 301 #if defined(CONFIG_PCI) 302 #ifndef CONFIG_PCI_PNP 303 static struct pci_config_table pci_mpc8568mds_config_table[] = { 304 { 305 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 306 pci_cfgfunc_config_device, 307 {PCI_ENET0_IOADDR, 308 PCI_ENET0_MEMADDR, 309 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} 310 }, 311 {} 312 }; 313 #endif 314 315 static struct pci_controller pci1_hose = { 316 #ifndef CONFIG_PCI_PNP 317 config_table: pci_mpc8568mds_config_table, 318 #endif 319 }; 320 #endif /* CONFIG_PCI */ 321 322 #ifdef CONFIG_PCIE1 323 static struct pci_controller pcie1_hose; 324 #endif /* CONFIG_PCIE1 */ 325 326 extern int fsl_pci_setup_inbound_windows(struct pci_region *r); 327 extern void fsl_pci_init(struct pci_controller *hose); 328 329 int first_free_busno = 0; 330 331 /* 332 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board 333 */ 334 void 335 pib_init(void) 336 { 337 u8 val8, orig_i2c_bus; 338 /* 339 * Assign PIB PMC2/3 to PCI bus 340 */ 341 342 /*switch temporarily to I2C bus #2 */ 343 orig_i2c_bus = i2c_get_bus_num(); 344 i2c_set_bus_num(1); 345 346 val8 = 0x00; 347 i2c_write(0x23, 0x6, 1, &val8, 1); 348 i2c_write(0x23, 0x7, 1, &val8, 1); 349 val8 = 0xff; 350 i2c_write(0x23, 0x2, 1, &val8, 1); 351 i2c_write(0x23, 0x3, 1, &val8, 1); 352 353 val8 = 0x00; 354 i2c_write(0x26, 0x6, 1, &val8, 1); 355 val8 = 0x34; 356 i2c_write(0x26, 0x7, 1, &val8, 1); 357 val8 = 0xf9; 358 i2c_write(0x26, 0x2, 1, &val8, 1); 359 val8 = 0xff; 360 i2c_write(0x26, 0x3, 1, &val8, 1); 361 362 val8 = 0x00; 363 i2c_write(0x27, 0x6, 1, &val8, 1); 364 i2c_write(0x27, 0x7, 1, &val8, 1); 365 val8 = 0xff; 366 i2c_write(0x27, 0x2, 1, &val8, 1); 367 val8 = 0xef; 368 i2c_write(0x27, 0x3, 1, &val8, 1); 369 370 asm("eieio"); 371 } 372 373 #ifdef CONFIG_PCI 374 void 375 pci_init_board(void) 376 { 377 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 378 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 379 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 380 381 #ifdef CONFIG_PCI1 382 { 383 pib_init(); 384 385 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 386 struct pci_controller *hose = &pci1_hose; 387 struct pci_region *r = hose->regions; 388 389 uint pci_32 = 1; /* PORDEVSR[15] */ 390 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 391 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 392 393 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); 394 395 uint pci_speed = 66666000; 396 397 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 398 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", 399 (pci_32) ? 32 : 64, 400 (pci_speed == 33333000) ? "33" : 401 (pci_speed == 66666000) ? "66" : "unknown", 402 pci_clk_sel ? "sync" : "async", 403 pci_agent ? "agent" : "host", 404 pci_arb ? "arbiter" : "external-arbiter" 405 ); 406 407 /* inbound */ 408 r += fsl_pci_setup_inbound_windows(r); 409 410 /* outbound memory */ 411 pci_set_region(r++, 412 CONFIG_SYS_PCI1_MEM_BASE, 413 CONFIG_SYS_PCI1_MEM_PHYS, 414 CONFIG_SYS_PCI1_MEM_SIZE, 415 PCI_REGION_MEM); 416 417 /* outbound io */ 418 pci_set_region(r++, 419 CONFIG_SYS_PCI1_IO_BASE, 420 CONFIG_SYS_PCI1_IO_PHYS, 421 CONFIG_SYS_PCI1_IO_SIZE, 422 PCI_REGION_IO); 423 424 hose->region_count = r - hose->regions; 425 426 hose->first_busno = first_free_busno; 427 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 428 429 fsl_pci_init(hose); 430 first_free_busno = hose->last_busno+1; 431 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 432 } else { 433 printf (" PCI: disabled\n"); 434 } 435 } 436 #else 437 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 438 #endif 439 440 #ifdef CONFIG_PCIE1 441 { 442 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 443 struct pci_controller *hose = &pcie1_hose; 444 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 445 struct pci_region *r = hose->regions; 446 447 int pcie_configured = io_sel >= 1; 448 449 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 450 printf ("\n PCIE connected to slot as %s (base address %x)", 451 pcie_ep ? "End Point" : "Root Complex", 452 (uint)pci); 453 454 if (pci->pme_msg_det) { 455 pci->pme_msg_det = 0xffffffff; 456 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 457 } 458 printf ("\n"); 459 460 /* inbound */ 461 r += fsl_pci_setup_inbound_windows(r); 462 463 /* outbound memory */ 464 pci_set_region(r++, 465 CONFIG_SYS_PCIE1_MEM_BASE, 466 CONFIG_SYS_PCIE1_MEM_PHYS, 467 CONFIG_SYS_PCIE1_MEM_SIZE, 468 PCI_REGION_MEM); 469 470 /* outbound io */ 471 pci_set_region(r++, 472 CONFIG_SYS_PCIE1_IO_BASE, 473 CONFIG_SYS_PCIE1_IO_PHYS, 474 CONFIG_SYS_PCIE1_IO_SIZE, 475 PCI_REGION_IO); 476 477 hose->region_count = r - hose->regions; 478 479 hose->first_busno=first_free_busno; 480 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 481 482 fsl_pci_init(hose); 483 printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 484 485 first_free_busno=hose->last_busno+1; 486 487 } else { 488 printf (" PCIE: disabled\n"); 489 } 490 } 491 #else 492 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 493 #endif 494 } 495 #endif /* CONFIG_PCI */ 496 497 #if defined(CONFIG_OF_BOARD_SETUP) 498 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, 499 struct pci_controller *hose); 500 501 void ft_board_setup(void *blob, bd_t *bd) 502 { 503 ft_cpu_setup(blob, bd); 504 505 #ifdef CONFIG_PCI1 506 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 507 #endif 508 #ifdef CONFIG_PCIE1 509 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 510 #endif 511 } 512 #endif 513