1 /* 2 * Copyright 2007 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/immap_fsl_pci.h> 30 #include <spd_sdram.h> 31 #include <i2c.h> 32 #include <ioports.h> 33 #include <libfdt.h> 34 #include <fdt_support.h> 35 36 #include "bcsr.h" 37 38 const qe_iop_conf_t qe_iop_conf_tab[] = { 39 /* GETH1 */ 40 {4, 10, 1, 0, 2}, /* TxD0 */ 41 {4, 9, 1, 0, 2}, /* TxD1 */ 42 {4, 8, 1, 0, 2}, /* TxD2 */ 43 {4, 7, 1, 0, 2}, /* TxD3 */ 44 {4, 23, 1, 0, 2}, /* TxD4 */ 45 {4, 22, 1, 0, 2}, /* TxD5 */ 46 {4, 21, 1, 0, 2}, /* TxD6 */ 47 {4, 20, 1, 0, 2}, /* TxD7 */ 48 {4, 15, 2, 0, 2}, /* RxD0 */ 49 {4, 14, 2, 0, 2}, /* RxD1 */ 50 {4, 13, 2, 0, 2}, /* RxD2 */ 51 {4, 12, 2, 0, 2}, /* RxD3 */ 52 {4, 29, 2, 0, 2}, /* RxD4 */ 53 {4, 28, 2, 0, 2}, /* RxD5 */ 54 {4, 27, 2, 0, 2}, /* RxD6 */ 55 {4, 26, 2, 0, 2}, /* RxD7 */ 56 {4, 11, 1, 0, 2}, /* TX_EN */ 57 {4, 24, 1, 0, 2}, /* TX_ER */ 58 {4, 16, 2, 0, 2}, /* RX_DV */ 59 {4, 30, 2, 0, 2}, /* RX_ER */ 60 {4, 17, 2, 0, 2}, /* RX_CLK */ 61 {4, 19, 1, 0, 2}, /* GTX_CLK */ 62 {1, 31, 2, 0, 3}, /* GTX125 */ 63 64 /* GETH2 */ 65 {5, 10, 1, 0, 2}, /* TxD0 */ 66 {5, 9, 1, 0, 2}, /* TxD1 */ 67 {5, 8, 1, 0, 2}, /* TxD2 */ 68 {5, 7, 1, 0, 2}, /* TxD3 */ 69 {5, 23, 1, 0, 2}, /* TxD4 */ 70 {5, 22, 1, 0, 2}, /* TxD5 */ 71 {5, 21, 1, 0, 2}, /* TxD6 */ 72 {5, 20, 1, 0, 2}, /* TxD7 */ 73 {5, 15, 2, 0, 2}, /* RxD0 */ 74 {5, 14, 2, 0, 2}, /* RxD1 */ 75 {5, 13, 2, 0, 2}, /* RxD2 */ 76 {5, 12, 2, 0, 2}, /* RxD3 */ 77 {5, 29, 2, 0, 2}, /* RxD4 */ 78 {5, 28, 2, 0, 2}, /* RxD5 */ 79 {5, 27, 2, 0, 3}, /* RxD6 */ 80 {5, 26, 2, 0, 2}, /* RxD7 */ 81 {5, 11, 1, 0, 2}, /* TX_EN */ 82 {5, 24, 1, 0, 2}, /* TX_ER */ 83 {5, 16, 2, 0, 2}, /* RX_DV */ 84 {5, 30, 2, 0, 2}, /* RX_ER */ 85 {5, 17, 2, 0, 2}, /* RX_CLK */ 86 {5, 19, 1, 0, 2}, /* GTX_CLK */ 87 {1, 31, 2, 0, 3}, /* GTX125 */ 88 {4, 6, 3, 0, 2}, /* MDIO */ 89 {4, 5, 1, 0, 2}, /* MDC */ 90 91 /* UART1 */ 92 {2, 0, 1, 0, 2}, /* UART_SOUT1 */ 93 {2, 1, 1, 0, 2}, /* UART_RTS1 */ 94 {2, 2, 2, 0, 2}, /* UART_CTS1 */ 95 {2, 3, 2, 0, 2}, /* UART_SIN1 */ 96 97 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 98 }; 99 100 101 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 102 extern void ddr_enable_ecc(unsigned int dram_size); 103 #endif 104 105 void local_bus_init(void); 106 void sdram_init(void); 107 108 int board_early_init_f (void) 109 { 110 /* 111 * Initialize local bus. 112 */ 113 local_bus_init (); 114 115 enable_8568mds_duart(); 116 enable_8568mds_flash_write(); 117 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 118 reset_8568mds_uccs(); 119 #endif 120 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) 121 enable_8568mds_qe_mdio(); 122 #endif 123 124 #ifdef CFG_I2C2_OFFSET 125 /* Enable I2C2_SCL and I2C2_SDA */ 126 volatile struct par_io *port_c; 127 port_c = (struct par_io*)(CFG_IMMR + 0xe0140); 128 port_c->cpdir2 |= 0x0f000000; 129 port_c->cppar2 &= ~0x0f000000; 130 port_c->cppar2 |= 0x0a000000; 131 #endif 132 133 return 0; 134 } 135 136 int checkboard (void) 137 { 138 printf ("Board: 8568 MDS\n"); 139 140 return 0; 141 } 142 143 phys_size_t 144 initdram(int board_type) 145 { 146 long dram_size = 0; 147 148 puts("Initializing\n"); 149 150 #if defined(CONFIG_DDR_DLL) 151 { 152 /* 153 * Work around to stabilize DDR DLL MSYNC_IN. 154 * Errata DDR9 seems to have been fixed. 155 * This is now the workaround for Errata DDR11: 156 * Override DLL = 1, Course Adj = 1, Tap Select = 0 157 */ 158 159 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 160 161 gur->ddrdllcr = 0x81000000; 162 asm("sync;isync;msync"); 163 udelay(200); 164 } 165 #endif 166 dram_size = spd_sdram(); 167 168 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 169 /* 170 * Initialize and enable DDR ECC. 171 */ 172 ddr_enable_ecc(dram_size); 173 #endif 174 /* 175 * SDRAM Initialization 176 */ 177 sdram_init(); 178 179 puts(" DDR: "); 180 return dram_size; 181 } 182 183 /* 184 * Initialize Local Bus 185 */ 186 void 187 local_bus_init(void) 188 { 189 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 190 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 191 192 uint clkdiv; 193 uint lbc_hz; 194 sys_info_t sysinfo; 195 196 get_sys_info(&sysinfo); 197 clkdiv = (lbc->lcrr & 0x0f) * 2; 198 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 199 200 gur->lbiuiplldcr1 = 0x00078080; 201 if (clkdiv == 16) { 202 gur->lbiuiplldcr0 = 0x7c0f1bf0; 203 } else if (clkdiv == 8) { 204 gur->lbiuiplldcr0 = 0x6c0f1bf0; 205 } else if (clkdiv == 4) { 206 gur->lbiuiplldcr0 = 0x5c0f1bf0; 207 } 208 209 lbc->lcrr |= 0x00030000; 210 211 asm("sync;isync;msync"); 212 } 213 214 /* 215 * Initialize SDRAM memory on the Local Bus. 216 */ 217 void 218 sdram_init(void) 219 { 220 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) 221 222 uint idx; 223 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 224 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 225 uint lsdmr_common; 226 227 puts(" SDRAM: "); 228 229 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 230 231 /* 232 * Setup SDRAM Base and Option Registers 233 */ 234 lbc->or2 = CFG_OR2_PRELIM; 235 asm("msync"); 236 237 lbc->br2 = CFG_BR2_PRELIM; 238 asm("msync"); 239 240 lbc->lbcr = CFG_LBC_LBCR; 241 asm("msync"); 242 243 244 lbc->lsrt = CFG_LBC_LSRT; 245 lbc->mrtpr = CFG_LBC_MRTPR; 246 asm("msync"); 247 248 /* 249 * MPC8568 uses "new" 15-16 style addressing. 250 */ 251 lsdmr_common = CFG_LBC_LSDMR_COMMON; 252 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; 253 254 /* 255 * Issue PRECHARGE ALL command. 256 */ 257 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; 258 asm("sync;msync"); 259 *sdram_addr = 0xff; 260 ppcDcbf((unsigned long) sdram_addr); 261 udelay(100); 262 263 /* 264 * Issue 8 AUTO REFRESH commands. 265 */ 266 for (idx = 0; idx < 8; idx++) { 267 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; 268 asm("sync;msync"); 269 *sdram_addr = 0xff; 270 ppcDcbf((unsigned long) sdram_addr); 271 udelay(100); 272 } 273 274 /* 275 * Issue 8 MODE-set command. 276 */ 277 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; 278 asm("sync;msync"); 279 *sdram_addr = 0xff; 280 ppcDcbf((unsigned long) sdram_addr); 281 udelay(100); 282 283 /* 284 * Issue NORMAL OP command. 285 */ 286 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; 287 asm("sync;msync"); 288 *sdram_addr = 0xff; 289 ppcDcbf((unsigned long) sdram_addr); 290 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 291 292 #endif /* enable SDRAM init */ 293 } 294 295 #if defined(CONFIG_PCI) 296 #ifndef CONFIG_PCI_PNP 297 static struct pci_config_table pci_mpc8568mds_config_table[] = { 298 { 299 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 300 pci_cfgfunc_config_device, 301 {PCI_ENET0_IOADDR, 302 PCI_ENET0_MEMADDR, 303 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} 304 }, 305 {} 306 }; 307 #endif 308 309 static struct pci_controller pci1_hose = { 310 #ifndef CONFIG_PCI_PNP 311 config_table: pci_mpc8568mds_config_table, 312 #endif 313 }; 314 #endif /* CONFIG_PCI */ 315 316 #ifdef CONFIG_PCIE1 317 static struct pci_controller pcie1_hose; 318 #endif /* CONFIG_PCIE1 */ 319 320 int first_free_busno = 0; 321 322 /* 323 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board 324 */ 325 void 326 pib_init(void) 327 { 328 u8 val8, orig_i2c_bus; 329 /* 330 * Assign PIB PMC2/3 to PCI bus 331 */ 332 333 /*switch temporarily to I2C bus #2 */ 334 orig_i2c_bus = i2c_get_bus_num(); 335 i2c_set_bus_num(1); 336 337 val8 = 0x00; 338 i2c_write(0x23, 0x6, 1, &val8, 1); 339 i2c_write(0x23, 0x7, 1, &val8, 1); 340 val8 = 0xff; 341 i2c_write(0x23, 0x2, 1, &val8, 1); 342 i2c_write(0x23, 0x3, 1, &val8, 1); 343 344 val8 = 0x00; 345 i2c_write(0x26, 0x6, 1, &val8, 1); 346 val8 = 0x34; 347 i2c_write(0x26, 0x7, 1, &val8, 1); 348 val8 = 0xf9; 349 i2c_write(0x26, 0x2, 1, &val8, 1); 350 val8 = 0xff; 351 i2c_write(0x26, 0x3, 1, &val8, 1); 352 353 val8 = 0x00; 354 i2c_write(0x27, 0x6, 1, &val8, 1); 355 i2c_write(0x27, 0x7, 1, &val8, 1); 356 val8 = 0xff; 357 i2c_write(0x27, 0x2, 1, &val8, 1); 358 val8 = 0xef; 359 i2c_write(0x27, 0x3, 1, &val8, 1); 360 361 asm("eieio"); 362 } 363 364 #ifdef CONFIG_PCI 365 void 366 pci_init_board(void) 367 { 368 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 369 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 370 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 371 372 #ifdef CONFIG_PCI1 373 { 374 pib_init(); 375 376 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 377 extern void fsl_pci_init(struct pci_controller *hose); 378 struct pci_controller *hose = &pci1_hose; 379 380 uint pci_32 = 1; /* PORDEVSR[15] */ 381 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 382 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 383 384 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); 385 386 uint pci_speed = 66666000; 387 388 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 389 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", 390 (pci_32) ? 32 : 64, 391 (pci_speed == 33333000) ? "33" : 392 (pci_speed == 66666000) ? "66" : "unknown", 393 pci_clk_sel ? "sync" : "async", 394 pci_agent ? "agent" : "host", 395 pci_arb ? "arbiter" : "external-arbiter" 396 ); 397 398 /* inbound */ 399 pci_set_region(hose->regions + 0, 400 CFG_PCI_MEMORY_BUS, 401 CFG_PCI_MEMORY_PHYS, 402 CFG_PCI_MEMORY_SIZE, 403 PCI_REGION_MEM | PCI_REGION_MEMORY); 404 405 /* outbound memory */ 406 pci_set_region(hose->regions + 1, 407 CFG_PCI1_MEM_BASE, 408 CFG_PCI1_MEM_PHYS, 409 CFG_PCI1_MEM_SIZE, 410 PCI_REGION_MEM); 411 412 /* outbound io */ 413 pci_set_region(hose->regions + 2, 414 CFG_PCI1_IO_BASE, 415 CFG_PCI1_IO_PHYS, 416 CFG_PCI1_IO_SIZE, 417 PCI_REGION_IO); 418 419 hose->region_count = 3; 420 421 hose->first_busno = first_free_busno; 422 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 423 424 fsl_pci_init(hose); 425 first_free_busno = hose->last_busno+1; 426 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 427 } else { 428 printf (" PCI: disabled\n"); 429 } 430 } 431 #else 432 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 433 #endif 434 435 #ifdef CONFIG_PCIE1 436 { 437 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 438 extern void fsl_pci_init(struct pci_controller *hose); 439 struct pci_controller *hose = &pcie1_hose; 440 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 441 442 int pcie_configured = io_sel >= 1; 443 444 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 445 printf ("\n PCIE connected to slot as %s (base address %x)", 446 pcie_ep ? "End Point" : "Root Complex", 447 (uint)pci); 448 449 if (pci->pme_msg_det) { 450 pci->pme_msg_det = 0xffffffff; 451 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 452 } 453 printf ("\n"); 454 455 /* inbound */ 456 pci_set_region(hose->regions + 0, 457 CFG_PCI_MEMORY_BUS, 458 CFG_PCI_MEMORY_PHYS, 459 CFG_PCI_MEMORY_SIZE, 460 PCI_REGION_MEM | PCI_REGION_MEMORY); 461 462 /* outbound memory */ 463 pci_set_region(hose->regions + 1, 464 CFG_PCIE1_MEM_BASE, 465 CFG_PCIE1_MEM_PHYS, 466 CFG_PCIE1_MEM_SIZE, 467 PCI_REGION_MEM); 468 469 /* outbound io */ 470 pci_set_region(hose->regions + 2, 471 CFG_PCIE1_IO_BASE, 472 CFG_PCIE1_IO_PHYS, 473 CFG_PCIE1_IO_SIZE, 474 PCI_REGION_IO); 475 476 hose->region_count = 3; 477 478 hose->first_busno=first_free_busno; 479 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 480 481 fsl_pci_init(hose); 482 printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 483 484 first_free_busno=hose->last_busno+1; 485 486 } else { 487 printf (" PCIE: disabled\n"); 488 } 489 } 490 #else 491 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 492 #endif 493 } 494 #endif /* CONFIG_PCI */ 495 496 #if defined(CONFIG_OF_BOARD_SETUP) 497 void 498 ft_board_setup(void *blob, bd_t *bd) 499 { 500 int node, tmp[2]; 501 const char *path; 502 503 ft_cpu_setup(blob, bd); 504 505 node = fdt_path_offset(blob, "/aliases"); 506 tmp[0] = 0; 507 if (node >= 0) { 508 #ifdef CONFIG_PCI1 509 path = fdt_getprop(blob, node, "pci0", NULL); 510 if (path) { 511 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 512 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 513 } 514 #endif 515 #ifdef CONFIG_PCIE1 516 path = fdt_getprop(blob, node, "pci1", NULL); 517 if (path) { 518 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 519 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 520 } 521 #endif 522 } 523 } 524 #endif 525