1 /* 2 * Copyright 2007 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/immap_fsl_pci.h> 30 #include <spd.h> 31 #include <i2c.h> 32 #include <ioports.h> 33 #include <libfdt.h> 34 #include <fdt_support.h> 35 36 #include "bcsr.h" 37 38 const qe_iop_conf_t qe_iop_conf_tab[] = { 39 /* GETH1 */ 40 {4, 10, 1, 0, 2}, /* TxD0 */ 41 {4, 9, 1, 0, 2}, /* TxD1 */ 42 {4, 8, 1, 0, 2}, /* TxD2 */ 43 {4, 7, 1, 0, 2}, /* TxD3 */ 44 {4, 23, 1, 0, 2}, /* TxD4 */ 45 {4, 22, 1, 0, 2}, /* TxD5 */ 46 {4, 21, 1, 0, 2}, /* TxD6 */ 47 {4, 20, 1, 0, 2}, /* TxD7 */ 48 {4, 15, 2, 0, 2}, /* RxD0 */ 49 {4, 14, 2, 0, 2}, /* RxD1 */ 50 {4, 13, 2, 0, 2}, /* RxD2 */ 51 {4, 12, 2, 0, 2}, /* RxD3 */ 52 {4, 29, 2, 0, 2}, /* RxD4 */ 53 {4, 28, 2, 0, 2}, /* RxD5 */ 54 {4, 27, 2, 0, 2}, /* RxD6 */ 55 {4, 26, 2, 0, 2}, /* RxD7 */ 56 {4, 11, 1, 0, 2}, /* TX_EN */ 57 {4, 24, 1, 0, 2}, /* TX_ER */ 58 {4, 16, 2, 0, 2}, /* RX_DV */ 59 {4, 30, 2, 0, 2}, /* RX_ER */ 60 {4, 17, 2, 0, 2}, /* RX_CLK */ 61 {4, 19, 1, 0, 2}, /* GTX_CLK */ 62 {1, 31, 2, 0, 3}, /* GTX125 */ 63 64 /* GETH2 */ 65 {5, 10, 1, 0, 2}, /* TxD0 */ 66 {5, 9, 1, 0, 2}, /* TxD1 */ 67 {5, 8, 1, 0, 2}, /* TxD2 */ 68 {5, 7, 1, 0, 2}, /* TxD3 */ 69 {5, 23, 1, 0, 2}, /* TxD4 */ 70 {5, 22, 1, 0, 2}, /* TxD5 */ 71 {5, 21, 1, 0, 2}, /* TxD6 */ 72 {5, 20, 1, 0, 2}, /* TxD7 */ 73 {5, 15, 2, 0, 2}, /* RxD0 */ 74 {5, 14, 2, 0, 2}, /* RxD1 */ 75 {5, 13, 2, 0, 2}, /* RxD2 */ 76 {5, 12, 2, 0, 2}, /* RxD3 */ 77 {5, 29, 2, 0, 2}, /* RxD4 */ 78 {5, 28, 2, 0, 2}, /* RxD5 */ 79 {5, 27, 2, 0, 3}, /* RxD6 */ 80 {5, 26, 2, 0, 2}, /* RxD7 */ 81 {5, 11, 1, 0, 2}, /* TX_EN */ 82 {5, 24, 1, 0, 2}, /* TX_ER */ 83 {5, 16, 2, 0, 2}, /* RX_DV */ 84 {5, 30, 2, 0, 2}, /* RX_ER */ 85 {5, 17, 2, 0, 2}, /* RX_CLK */ 86 {5, 19, 1, 0, 2}, /* GTX_CLK */ 87 {1, 31, 2, 0, 3}, /* GTX125 */ 88 {4, 6, 3, 0, 2}, /* MDIO */ 89 {4, 5, 1, 0, 2}, /* MDC */ 90 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 91 }; 92 93 94 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 95 extern void ddr_enable_ecc(unsigned int dram_size); 96 #endif 97 98 extern long int spd_sdram(void); 99 100 void local_bus_init(void); 101 void sdram_init(void); 102 103 int board_early_init_f (void) 104 { 105 /* 106 * Initialize local bus. 107 */ 108 local_bus_init (); 109 110 enable_8568mds_duart(); 111 enable_8568mds_flash_write(); 112 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) 113 enable_8568mds_qe_mdio(); 114 #endif 115 116 #ifdef CFG_I2C2_OFFSET 117 /* Enable I2C2_SCL and I2C2_SDA */ 118 volatile struct par_io *port_c; 119 port_c = (struct par_io*)(CFG_IMMR + 0xe0140); 120 port_c->cpdir2 |= 0x0f000000; 121 port_c->cppar2 &= ~0x0f000000; 122 port_c->cppar2 |= 0x0a000000; 123 #endif 124 125 return 0; 126 } 127 128 int checkboard (void) 129 { 130 printf ("Board: 8568 MDS\n"); 131 132 return 0; 133 } 134 135 long int 136 initdram(int board_type) 137 { 138 long dram_size = 0; 139 140 puts("Initializing\n"); 141 142 #if defined(CONFIG_DDR_DLL) 143 { 144 /* 145 * Work around to stabilize DDR DLL MSYNC_IN. 146 * Errata DDR9 seems to have been fixed. 147 * This is now the workaround for Errata DDR11: 148 * Override DLL = 1, Course Adj = 1, Tap Select = 0 149 */ 150 151 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 152 153 gur->ddrdllcr = 0x81000000; 154 asm("sync;isync;msync"); 155 udelay(200); 156 } 157 #endif 158 dram_size = spd_sdram(); 159 160 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 161 /* 162 * Initialize and enable DDR ECC. 163 */ 164 ddr_enable_ecc(dram_size); 165 #endif 166 /* 167 * SDRAM Initialization 168 */ 169 sdram_init(); 170 171 puts(" DDR: "); 172 return dram_size; 173 } 174 175 /* 176 * Initialize Local Bus 177 */ 178 void 179 local_bus_init(void) 180 { 181 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 182 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 183 184 uint clkdiv; 185 uint lbc_hz; 186 sys_info_t sysinfo; 187 188 get_sys_info(&sysinfo); 189 clkdiv = (lbc->lcrr & 0x0f) * 2; 190 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 191 192 gur->lbiuiplldcr1 = 0x00078080; 193 if (clkdiv == 16) { 194 gur->lbiuiplldcr0 = 0x7c0f1bf0; 195 } else if (clkdiv == 8) { 196 gur->lbiuiplldcr0 = 0x6c0f1bf0; 197 } else if (clkdiv == 4) { 198 gur->lbiuiplldcr0 = 0x5c0f1bf0; 199 } 200 201 lbc->lcrr |= 0x00030000; 202 203 asm("sync;isync;msync"); 204 } 205 206 /* 207 * Initialize SDRAM memory on the Local Bus. 208 */ 209 void 210 sdram_init(void) 211 { 212 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) 213 214 uint idx; 215 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 216 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 217 uint lsdmr_common; 218 219 puts(" SDRAM: "); 220 221 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 222 223 /* 224 * Setup SDRAM Base and Option Registers 225 */ 226 lbc->or2 = CFG_OR2_PRELIM; 227 asm("msync"); 228 229 lbc->br2 = CFG_BR2_PRELIM; 230 asm("msync"); 231 232 lbc->lbcr = CFG_LBC_LBCR; 233 asm("msync"); 234 235 236 lbc->lsrt = CFG_LBC_LSRT; 237 lbc->mrtpr = CFG_LBC_MRTPR; 238 asm("msync"); 239 240 /* 241 * MPC8568 uses "new" 15-16 style addressing. 242 */ 243 lsdmr_common = CFG_LBC_LSDMR_COMMON; 244 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; 245 246 /* 247 * Issue PRECHARGE ALL command. 248 */ 249 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; 250 asm("sync;msync"); 251 *sdram_addr = 0xff; 252 ppcDcbf((unsigned long) sdram_addr); 253 udelay(100); 254 255 /* 256 * Issue 8 AUTO REFRESH commands. 257 */ 258 for (idx = 0; idx < 8; idx++) { 259 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; 260 asm("sync;msync"); 261 *sdram_addr = 0xff; 262 ppcDcbf((unsigned long) sdram_addr); 263 udelay(100); 264 } 265 266 /* 267 * Issue 8 MODE-set command. 268 */ 269 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; 270 asm("sync;msync"); 271 *sdram_addr = 0xff; 272 ppcDcbf((unsigned long) sdram_addr); 273 udelay(100); 274 275 /* 276 * Issue NORMAL OP command. 277 */ 278 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; 279 asm("sync;msync"); 280 *sdram_addr = 0xff; 281 ppcDcbf((unsigned long) sdram_addr); 282 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 283 284 #endif /* enable SDRAM init */ 285 } 286 287 #if defined(CFG_DRAM_TEST) 288 int 289 testdram(void) 290 { 291 uint *pstart = (uint *) CFG_MEMTEST_START; 292 uint *pend = (uint *) CFG_MEMTEST_END; 293 uint *p; 294 295 printf("Testing DRAM from 0x%08x to 0x%08x\n", 296 CFG_MEMTEST_START, 297 CFG_MEMTEST_END); 298 299 printf("DRAM test phase 1:\n"); 300 for (p = pstart; p < pend; p++) 301 *p = 0xaaaaaaaa; 302 303 for (p = pstart; p < pend; p++) { 304 if (*p != 0xaaaaaaaa) { 305 printf ("DRAM test fails at: %08x\n", (uint) p); 306 return 1; 307 } 308 } 309 310 printf("DRAM test phase 2:\n"); 311 for (p = pstart; p < pend; p++) 312 *p = 0x55555555; 313 314 for (p = pstart; p < pend; p++) { 315 if (*p != 0x55555555) { 316 printf ("DRAM test fails at: %08x\n", (uint) p); 317 return 1; 318 } 319 } 320 321 printf("DRAM test passed.\n"); 322 return 0; 323 } 324 #endif 325 326 #if defined(CONFIG_PCI) 327 #ifndef CONFIG_PCI_PNP 328 static struct pci_config_table pci_mpc8568mds_config_table[] = { 329 { 330 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 331 pci_cfgfunc_config_device, 332 {PCI_ENET0_IOADDR, 333 PCI_ENET0_MEMADDR, 334 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} 335 }, 336 {} 337 }; 338 #endif 339 340 static struct pci_controller pci1_hose = { 341 #ifndef CONFIG_PCI_PNP 342 config_table: pci_mpc8568mds_config_table, 343 #endif 344 }; 345 #endif /* CONFIG_PCI */ 346 347 #ifdef CONFIG_PCIE1 348 static struct pci_controller pcie1_hose; 349 #endif /* CONFIG_PCIE1 */ 350 351 int first_free_busno = 0; 352 353 /* 354 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board 355 */ 356 void 357 pib_init(void) 358 { 359 u8 val8, orig_i2c_bus; 360 /* 361 * Assign PIB PMC2/3 to PCI bus 362 */ 363 364 /*switch temporarily to I2C bus #2 */ 365 orig_i2c_bus = i2c_get_bus_num(); 366 i2c_set_bus_num(1); 367 368 val8 = 0x00; 369 i2c_write(0x23, 0x6, 1, &val8, 1); 370 i2c_write(0x23, 0x7, 1, &val8, 1); 371 val8 = 0xff; 372 i2c_write(0x23, 0x2, 1, &val8, 1); 373 i2c_write(0x23, 0x3, 1, &val8, 1); 374 375 val8 = 0x00; 376 i2c_write(0x26, 0x6, 1, &val8, 1); 377 val8 = 0x34; 378 i2c_write(0x26, 0x7, 1, &val8, 1); 379 val8 = 0xf9; 380 i2c_write(0x26, 0x2, 1, &val8, 1); 381 val8 = 0xff; 382 i2c_write(0x26, 0x3, 1, &val8, 1); 383 384 val8 = 0x00; 385 i2c_write(0x27, 0x6, 1, &val8, 1); 386 i2c_write(0x27, 0x7, 1, &val8, 1); 387 val8 = 0xff; 388 i2c_write(0x27, 0x2, 1, &val8, 1); 389 val8 = 0xef; 390 i2c_write(0x27, 0x3, 1, &val8, 1); 391 392 asm("eieio"); 393 } 394 395 #ifdef CONFIG_PCI 396 void 397 pci_init_board(void) 398 { 399 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 400 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 401 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 402 403 #ifdef CONFIG_PCI1 404 { 405 pib_init(); 406 407 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 408 extern void fsl_pci_init(struct pci_controller *hose); 409 struct pci_controller *hose = &pci1_hose; 410 411 uint pci_32 = 1; /* PORDEVSR[15] */ 412 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 413 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 414 415 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); 416 417 uint pci_speed = 66666000; 418 419 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 420 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", 421 (pci_32) ? 32 : 64, 422 (pci_speed == 33333000) ? "33" : 423 (pci_speed == 66666000) ? "66" : "unknown", 424 pci_clk_sel ? "sync" : "async", 425 pci_agent ? "agent" : "host", 426 pci_arb ? "arbiter" : "external-arbiter" 427 ); 428 429 /* inbound */ 430 pci_set_region(hose->regions + 0, 431 CFG_PCI_MEMORY_BUS, 432 CFG_PCI_MEMORY_PHYS, 433 CFG_PCI_MEMORY_SIZE, 434 PCI_REGION_MEM | PCI_REGION_MEMORY); 435 436 /* outbound memory */ 437 pci_set_region(hose->regions + 1, 438 CFG_PCI1_MEM_BASE, 439 CFG_PCI1_MEM_PHYS, 440 CFG_PCI1_MEM_SIZE, 441 PCI_REGION_MEM); 442 443 /* outbound io */ 444 pci_set_region(hose->regions + 2, 445 CFG_PCI1_IO_BASE, 446 CFG_PCI1_IO_PHYS, 447 CFG_PCI1_IO_SIZE, 448 PCI_REGION_IO); 449 450 hose->region_count = 3; 451 452 hose->first_busno = first_free_busno; 453 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 454 455 fsl_pci_init(hose); 456 first_free_busno = hose->last_busno+1; 457 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 458 } else { 459 printf (" PCI: disabled\n"); 460 } 461 } 462 #else 463 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 464 #endif 465 466 #ifdef CONFIG_PCIE1 467 { 468 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 469 extern void fsl_pci_init(struct pci_controller *hose); 470 struct pci_controller *hose = &pcie1_hose; 471 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 472 473 int pcie_configured = io_sel >= 1; 474 475 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 476 printf ("\n PCIE connected to slot as %s (base address %x)", 477 pcie_ep ? "End Point" : "Root Complex", 478 (uint)pci); 479 480 if (pci->pme_msg_det) { 481 pci->pme_msg_det = 0xffffffff; 482 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 483 } 484 printf ("\n"); 485 486 /* inbound */ 487 pci_set_region(hose->regions + 0, 488 CFG_PCI_MEMORY_BUS, 489 CFG_PCI_MEMORY_PHYS, 490 CFG_PCI_MEMORY_SIZE, 491 PCI_REGION_MEM | PCI_REGION_MEMORY); 492 493 /* outbound memory */ 494 pci_set_region(hose->regions + 1, 495 CFG_PCIE1_MEM_BASE, 496 CFG_PCIE1_MEM_PHYS, 497 CFG_PCIE1_MEM_SIZE, 498 PCI_REGION_MEM); 499 500 /* outbound io */ 501 pci_set_region(hose->regions + 2, 502 CFG_PCIE1_IO_BASE, 503 CFG_PCIE1_IO_PHYS, 504 CFG_PCIE1_IO_SIZE, 505 PCI_REGION_IO); 506 507 hose->region_count = 3; 508 509 hose->first_busno=first_free_busno; 510 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 511 512 fsl_pci_init(hose); 513 printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 514 515 first_free_busno=hose->last_busno+1; 516 517 } else { 518 printf (" PCIE: disabled\n"); 519 } 520 } 521 #else 522 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 523 #endif 524 } 525 #endif /* CONFIG_PCI */ 526 527 #if defined(CONFIG_OF_BOARD_SETUP) 528 void 529 ft_board_setup(void *blob, bd_t *bd) 530 { 531 int node, tmp[2]; 532 const char *path; 533 534 ft_cpu_setup(blob, bd); 535 536 node = fdt_path_offset(blob, "/aliases"); 537 tmp[0] = 0; 538 if (node >= 0) { 539 #ifdef CONFIG_PCI1 540 path = fdt_getprop(blob, node, "pci0", NULL); 541 if (path) { 542 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 543 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 544 } 545 #endif 546 #ifdef CONFIG_PCIE1 547 path = fdt_getprop(blob, node, "pci1", NULL); 548 if (path) { 549 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 550 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 551 } 552 #endif 553 } 554 } 555 #endif 556