1 /*
2  * Copyright 2007 Freescale Semiconductor.
3  *
4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #include <common.h>
26 #include <pci.h>
27 #include <asm/processor.h>
28 #include <asm/mmu.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <spd_sdram.h>
33 #include <i2c.h>
34 #include <ioports.h>
35 #include <libfdt.h>
36 #include <fdt_support.h>
37 
38 #include "bcsr.h"
39 
40 const qe_iop_conf_t qe_iop_conf_tab[] = {
41 	/* GETH1 */
42 	{4, 10, 1, 0, 2}, /* TxD0 */
43 	{4,  9, 1, 0, 2}, /* TxD1 */
44 	{4,  8, 1, 0, 2}, /* TxD2 */
45 	{4,  7, 1, 0, 2}, /* TxD3 */
46 	{4, 23, 1, 0, 2}, /* TxD4 */
47 	{4, 22, 1, 0, 2}, /* TxD5 */
48 	{4, 21, 1, 0, 2}, /* TxD6 */
49 	{4, 20, 1, 0, 2}, /* TxD7 */
50 	{4, 15, 2, 0, 2}, /* RxD0 */
51 	{4, 14, 2, 0, 2}, /* RxD1 */
52 	{4, 13, 2, 0, 2}, /* RxD2 */
53 	{4, 12, 2, 0, 2}, /* RxD3 */
54 	{4, 29, 2, 0, 2}, /* RxD4 */
55 	{4, 28, 2, 0, 2}, /* RxD5 */
56 	{4, 27, 2, 0, 2}, /* RxD6 */
57 	{4, 26, 2, 0, 2}, /* RxD7 */
58 	{4, 11, 1, 0, 2}, /* TX_EN */
59 	{4, 24, 1, 0, 2}, /* TX_ER */
60 	{4, 16, 2, 0, 2}, /* RX_DV */
61 	{4, 30, 2, 0, 2}, /* RX_ER */
62 	{4, 17, 2, 0, 2}, /* RX_CLK */
63 	{4, 19, 1, 0, 2}, /* GTX_CLK */
64 	{1, 31, 2, 0, 3}, /* GTX125 */
65 
66 	/* GETH2 */
67 	{5, 10, 1, 0, 2}, /* TxD0 */
68 	{5,  9, 1, 0, 2}, /* TxD1 */
69 	{5,  8, 1, 0, 2}, /* TxD2 */
70 	{5,  7, 1, 0, 2}, /* TxD3 */
71 	{5, 23, 1, 0, 2}, /* TxD4 */
72 	{5, 22, 1, 0, 2}, /* TxD5 */
73 	{5, 21, 1, 0, 2}, /* TxD6 */
74 	{5, 20, 1, 0, 2}, /* TxD7 */
75 	{5, 15, 2, 0, 2}, /* RxD0 */
76 	{5, 14, 2, 0, 2}, /* RxD1 */
77 	{5, 13, 2, 0, 2}, /* RxD2 */
78 	{5, 12, 2, 0, 2}, /* RxD3 */
79 	{5, 29, 2, 0, 2}, /* RxD4 */
80 	{5, 28, 2, 0, 2}, /* RxD5 */
81 	{5, 27, 2, 0, 3}, /* RxD6 */
82 	{5, 26, 2, 0, 2}, /* RxD7 */
83 	{5, 11, 1, 0, 2}, /* TX_EN */
84 	{5, 24, 1, 0, 2}, /* TX_ER */
85 	{5, 16, 2, 0, 2}, /* RX_DV */
86 	{5, 30, 2, 0, 2}, /* RX_ER */
87 	{5, 17, 2, 0, 2}, /* RX_CLK */
88 	{5, 19, 1, 0, 2}, /* GTX_CLK */
89 	{1, 31, 2, 0, 3}, /* GTX125 */
90 	{4,  6, 3, 0, 2}, /* MDIO */
91 	{4,  5, 1, 0, 2}, /* MDC */
92 
93 	/* UART1 */
94 	{2, 0, 1, 0, 2}, /* UART_SOUT1 */
95 	{2, 1, 1, 0, 2}, /* UART_RTS1 */
96 	{2, 2, 2, 0, 2}, /* UART_CTS1 */
97 	{2, 3, 2, 0, 2}, /* UART_SIN1 */
98 
99 	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
100 };
101 
102 void local_bus_init(void);
103 void sdram_init(void);
104 
105 int board_early_init_f (void)
106 {
107 	/*
108 	 * Initialize local bus.
109 	 */
110 	local_bus_init ();
111 
112 	enable_8568mds_duart();
113 	enable_8568mds_flash_write();
114 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
115 	reset_8568mds_uccs();
116 #endif
117 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
118 	enable_8568mds_qe_mdio();
119 #endif
120 
121 #ifdef CONFIG_SYS_I2C2_OFFSET
122 	/* Enable I2C2_SCL and I2C2_SDA */
123 	volatile struct par_io *port_c;
124 	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
125 	port_c->cpdir2 |= 0x0f000000;
126 	port_c->cppar2 &= ~0x0f000000;
127 	port_c->cppar2 |= 0x0a000000;
128 #endif
129 
130 	return 0;
131 }
132 
133 int checkboard (void)
134 {
135 	printf ("Board: 8568 MDS\n");
136 
137 	return 0;
138 }
139 
140 phys_size_t
141 initdram(int board_type)
142 {
143 	long dram_size = 0;
144 
145 	puts("Initializing\n");
146 
147 #if defined(CONFIG_DDR_DLL)
148 	{
149 		/*
150 		 * Work around to stabilize DDR DLL MSYNC_IN.
151 		 * Errata DDR9 seems to have been fixed.
152 		 * This is now the workaround for Errata DDR11:
153 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
154 		 */
155 
156 		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
157 
158 		gur->ddrdllcr = 0x81000000;
159 		asm("sync;isync;msync");
160 		udelay(200);
161 	}
162 #endif
163 
164 	dram_size = fsl_ddr_sdram();
165 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
166 	dram_size *= 0x100000;
167 
168 	/*
169 	 * SDRAM Initialization
170 	 */
171 	sdram_init();
172 
173 	puts("    DDR: ");
174 	return dram_size;
175 }
176 
177 /*
178  * Initialize Local Bus
179  */
180 void
181 local_bus_init(void)
182 {
183 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
184 	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
185 
186 	uint clkdiv;
187 	uint lbc_hz;
188 	sys_info_t sysinfo;
189 
190 	get_sys_info(&sysinfo);
191 	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
192 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
193 
194 	gur->lbiuiplldcr1 = 0x00078080;
195 	if (clkdiv == 16) {
196 		gur->lbiuiplldcr0 = 0x7c0f1bf0;
197 	} else if (clkdiv == 8) {
198 		gur->lbiuiplldcr0 = 0x6c0f1bf0;
199 	} else if (clkdiv == 4) {
200 		gur->lbiuiplldcr0 = 0x5c0f1bf0;
201 	}
202 
203 	lbc->lcrr |= 0x00030000;
204 
205 	asm("sync;isync;msync");
206 }
207 
208 /*
209  * Initialize SDRAM memory on the Local Bus.
210  */
211 void
212 sdram_init(void)
213 {
214 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
215 
216 	uint idx;
217 	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
218 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
219 	uint lsdmr_common;
220 
221 	puts("    SDRAM: ");
222 
223 	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
224 
225 	/*
226 	 * Setup SDRAM Base and Option Registers
227 	 */
228 	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
229 	asm("msync");
230 
231 	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
232 	asm("msync");
233 
234 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
235 	asm("msync");
236 
237 
238 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
239 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
240 	asm("msync");
241 
242 	/*
243 	 * MPC8568 uses "new" 15-16 style addressing.
244 	 */
245 	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
246 	lsdmr_common |= LSDMR_BSMA1516;
247 
248 	/*
249 	 * Issue PRECHARGE ALL command.
250 	 */
251 	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
252 	asm("sync;msync");
253 	*sdram_addr = 0xff;
254 	ppcDcbf((unsigned long) sdram_addr);
255 	udelay(100);
256 
257 	/*
258 	 * Issue 8 AUTO REFRESH commands.
259 	 */
260 	for (idx = 0; idx < 8; idx++) {
261 		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
262 		asm("sync;msync");
263 		*sdram_addr = 0xff;
264 		ppcDcbf((unsigned long) sdram_addr);
265 		udelay(100);
266 	}
267 
268 	/*
269 	 * Issue 8 MODE-set command.
270 	 */
271 	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
272 	asm("sync;msync");
273 	*sdram_addr = 0xff;
274 	ppcDcbf((unsigned long) sdram_addr);
275 	udelay(100);
276 
277 	/*
278 	 * Issue NORMAL OP command.
279 	 */
280 	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
281 	asm("sync;msync");
282 	*sdram_addr = 0xff;
283 	ppcDcbf((unsigned long) sdram_addr);
284 	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
285 
286 #endif	/* enable SDRAM init */
287 }
288 
289 #if defined(CONFIG_PCI)
290 #ifndef CONFIG_PCI_PNP
291 static struct pci_config_table pci_mpc8568mds_config_table[] = {
292 	{
293 	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
294 	 pci_cfgfunc_config_device,
295 	 {PCI_ENET0_IOADDR,
296 	  PCI_ENET0_MEMADDR,
297 	  PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
298 	 },
299 	{}
300 };
301 #endif
302 
303 static struct pci_controller pci1_hose = {
304 #ifndef CONFIG_PCI_PNP
305 	config_table: pci_mpc8568mds_config_table,
306 #endif
307 };
308 #endif	/* CONFIG_PCI */
309 
310 #ifdef CONFIG_PCIE1
311 static struct pci_controller pcie1_hose;
312 #endif  /* CONFIG_PCIE1 */
313 
314 int first_free_busno = 0;
315 
316 /*
317  * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
318  */
319 void
320 pib_init(void)
321 {
322 	u8 val8, orig_i2c_bus;
323 	/*
324 	 * Assign PIB PMC2/3 to PCI bus
325 	 */
326 
327 	/*switch temporarily to I2C bus #2 */
328 	orig_i2c_bus = i2c_get_bus_num();
329 	i2c_set_bus_num(1);
330 
331 	val8 = 0x00;
332 	i2c_write(0x23, 0x6, 1, &val8, 1);
333 	i2c_write(0x23, 0x7, 1, &val8, 1);
334 	val8 = 0xff;
335 	i2c_write(0x23, 0x2, 1, &val8, 1);
336 	i2c_write(0x23, 0x3, 1, &val8, 1);
337 
338 	val8 = 0x00;
339 	i2c_write(0x26, 0x6, 1, &val8, 1);
340 	val8 = 0x34;
341 	i2c_write(0x26, 0x7, 1, &val8, 1);
342 	val8 = 0xf9;
343 	i2c_write(0x26, 0x2, 1, &val8, 1);
344 	val8 = 0xff;
345 	i2c_write(0x26, 0x3, 1, &val8, 1);
346 
347 	val8 = 0x00;
348 	i2c_write(0x27, 0x6, 1, &val8, 1);
349 	i2c_write(0x27, 0x7, 1, &val8, 1);
350 	val8 = 0xff;
351 	i2c_write(0x27, 0x2, 1, &val8, 1);
352 	val8 = 0xef;
353 	i2c_write(0x27, 0x3, 1, &val8, 1);
354 
355 	asm("eieio");
356 }
357 
358 #ifdef CONFIG_PCI
359 void
360 pci_init_board(void)
361 {
362 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
363 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
364 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
365 
366 #ifdef CONFIG_PCI1
367 {
368 	pib_init();
369 
370 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
371 	struct pci_controller *hose = &pci1_hose;
372 	struct pci_region *r = hose->regions;
373 
374 	uint pci_32 = 1;      /* PORDEVSR[15] */
375 	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
376 	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
377 
378 	uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
379 
380 	uint pci_speed = 66666000;
381 
382 	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
383 		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
384 			(pci_32) ? 32 : 64,
385 			(pci_speed == 33333000) ? "33" :
386 			(pci_speed == 66666000) ? "66" : "unknown",
387 			pci_clk_sel ? "sync" : "async",
388 			pci_agent ? "agent" : "host",
389 			pci_arb ? "arbiter" : "external-arbiter"
390 			);
391 
392 		/* outbound memory */
393 		pci_set_region(r++,
394 				CONFIG_SYS_PCI1_MEM_BUS,
395 				CONFIG_SYS_PCI1_MEM_PHYS,
396 				CONFIG_SYS_PCI1_MEM_SIZE,
397 				PCI_REGION_MEM);
398 
399 		/* outbound io */
400 		pci_set_region(r++,
401 				CONFIG_SYS_PCI1_IO_BUS,
402 				CONFIG_SYS_PCI1_IO_PHYS,
403 				CONFIG_SYS_PCI1_IO_SIZE,
404 				PCI_REGION_IO);
405 
406 		hose->region_count = r - hose->regions;
407 
408 		hose->first_busno = first_free_busno;
409 
410 		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
411 		first_free_busno = hose->last_busno+1;
412 		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
413 	} else {
414 	printf ("    PCI: disabled\n");
415 	}
416 }
417 #else
418 	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
419 #endif
420 
421 #ifdef CONFIG_PCIE1
422 {
423 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
424 	struct pci_controller *hose = &pcie1_hose;
425 	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
426 	struct pci_region *r = hose->regions;
427 
428 	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
429 
430 	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
431 		printf ("\n    PCIE connected to slot as %s (base address %x)",
432 			pcie_ep ? "End Point" : "Root Complex",
433 			(uint)pci);
434 
435 		if (pci->pme_msg_det) {
436 			pci->pme_msg_det = 0xffffffff;
437 			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
438 		}
439 		printf ("\n");
440 
441 		/* outbound memory */
442 		pci_set_region(r++,
443 				CONFIG_SYS_PCIE1_MEM_BUS,
444 				CONFIG_SYS_PCIE1_MEM_PHYS,
445 				CONFIG_SYS_PCIE1_MEM_SIZE,
446 				PCI_REGION_MEM);
447 
448 		/* outbound io */
449 		pci_set_region(r++,
450 				CONFIG_SYS_PCIE1_IO_BUS,
451 				CONFIG_SYS_PCIE1_IO_PHYS,
452 				CONFIG_SYS_PCIE1_IO_SIZE,
453 				PCI_REGION_IO);
454 
455 		hose->region_count = r - hose->regions;
456 
457 		hose->first_busno=first_free_busno;
458 
459 		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
460 		printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
461 
462 		first_free_busno=hose->last_busno+1;
463 
464 	} else {
465 		printf ("    PCIE: disabled\n");
466 	}
467 }
468 #else
469 	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
470 #endif
471 }
472 #endif /* CONFIG_PCI */
473 
474 #if defined(CONFIG_OF_BOARD_SETUP)
475 void ft_board_setup(void *blob, bd_t *bd)
476 {
477 	ft_cpu_setup(blob, bd);
478 
479 #ifdef CONFIG_PCI1
480 	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
481 #endif
482 #ifdef CONFIG_PCIE1
483 	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
484 #endif
485 }
486 #endif
487