1 /* 2 * Copyright 2007 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/immap_fsl_pci.h> 30 #include <spd.h> 31 #include <i2c.h> 32 #include <ioports.h> 33 #include <libfdt.h> 34 #include <fdt_support.h> 35 36 #include "bcsr.h" 37 38 const qe_iop_conf_t qe_iop_conf_tab[] = { 39 /* GETH1 */ 40 {4, 10, 1, 0, 2}, /* TxD0 */ 41 {4, 9, 1, 0, 2}, /* TxD1 */ 42 {4, 8, 1, 0, 2}, /* TxD2 */ 43 {4, 7, 1, 0, 2}, /* TxD3 */ 44 {4, 23, 1, 0, 2}, /* TxD4 */ 45 {4, 22, 1, 0, 2}, /* TxD5 */ 46 {4, 21, 1, 0, 2}, /* TxD6 */ 47 {4, 20, 1, 0, 2}, /* TxD7 */ 48 {4, 15, 2, 0, 2}, /* RxD0 */ 49 {4, 14, 2, 0, 2}, /* RxD1 */ 50 {4, 13, 2, 0, 2}, /* RxD2 */ 51 {4, 12, 2, 0, 2}, /* RxD3 */ 52 {4, 29, 2, 0, 2}, /* RxD4 */ 53 {4, 28, 2, 0, 2}, /* RxD5 */ 54 {4, 27, 2, 0, 2}, /* RxD6 */ 55 {4, 26, 2, 0, 2}, /* RxD7 */ 56 {4, 11, 1, 0, 2}, /* TX_EN */ 57 {4, 24, 1, 0, 2}, /* TX_ER */ 58 {4, 16, 2, 0, 2}, /* RX_DV */ 59 {4, 30, 2, 0, 2}, /* RX_ER */ 60 {4, 17, 2, 0, 2}, /* RX_CLK */ 61 {4, 19, 1, 0, 2}, /* GTX_CLK */ 62 {1, 31, 2, 0, 3}, /* GTX125 */ 63 64 /* GETH2 */ 65 {5, 10, 1, 0, 2}, /* TxD0 */ 66 {5, 9, 1, 0, 2}, /* TxD1 */ 67 {5, 8, 1, 0, 2}, /* TxD2 */ 68 {5, 7, 1, 0, 2}, /* TxD3 */ 69 {5, 23, 1, 0, 2}, /* TxD4 */ 70 {5, 22, 1, 0, 2}, /* TxD5 */ 71 {5, 21, 1, 0, 2}, /* TxD6 */ 72 {5, 20, 1, 0, 2}, /* TxD7 */ 73 {5, 15, 2, 0, 2}, /* RxD0 */ 74 {5, 14, 2, 0, 2}, /* RxD1 */ 75 {5, 13, 2, 0, 2}, /* RxD2 */ 76 {5, 12, 2, 0, 2}, /* RxD3 */ 77 {5, 29, 2, 0, 2}, /* RxD4 */ 78 {5, 28, 2, 0, 2}, /* RxD5 */ 79 {5, 27, 2, 0, 3}, /* RxD6 */ 80 {5, 26, 2, 0, 2}, /* RxD7 */ 81 {5, 11, 1, 0, 2}, /* TX_EN */ 82 {5, 24, 1, 0, 2}, /* TX_ER */ 83 {5, 16, 2, 0, 2}, /* RX_DV */ 84 {5, 30, 2, 0, 2}, /* RX_ER */ 85 {5, 17, 2, 0, 2}, /* RX_CLK */ 86 {5, 19, 1, 0, 2}, /* GTX_CLK */ 87 {1, 31, 2, 0, 3}, /* GTX125 */ 88 {4, 6, 3, 0, 2}, /* MDIO */ 89 {4, 5, 1, 0, 2}, /* MDC */ 90 91 /* UART1 */ 92 {2, 0, 1, 0, 2}, /* UART_SOUT1 */ 93 {2, 1, 1, 0, 2}, /* UART_RTS1 */ 94 {2, 2, 2, 0, 2}, /* UART_CTS1 */ 95 {2, 3, 2, 0, 2}, /* UART_SIN1 */ 96 97 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 98 }; 99 100 101 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 102 extern void ddr_enable_ecc(unsigned int dram_size); 103 #endif 104 105 extern long int spd_sdram(void); 106 107 void local_bus_init(void); 108 void sdram_init(void); 109 110 int board_early_init_f (void) 111 { 112 /* 113 * Initialize local bus. 114 */ 115 local_bus_init (); 116 117 enable_8568mds_duart(); 118 enable_8568mds_flash_write(); 119 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 120 reset_8568mds_uccs(); 121 #endif 122 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) 123 enable_8568mds_qe_mdio(); 124 #endif 125 126 #ifdef CFG_I2C2_OFFSET 127 /* Enable I2C2_SCL and I2C2_SDA */ 128 volatile struct par_io *port_c; 129 port_c = (struct par_io*)(CFG_IMMR + 0xe0140); 130 port_c->cpdir2 |= 0x0f000000; 131 port_c->cppar2 &= ~0x0f000000; 132 port_c->cppar2 |= 0x0a000000; 133 #endif 134 135 return 0; 136 } 137 138 int checkboard (void) 139 { 140 printf ("Board: 8568 MDS\n"); 141 142 return 0; 143 } 144 145 long int 146 initdram(int board_type) 147 { 148 long dram_size = 0; 149 150 puts("Initializing\n"); 151 152 #if defined(CONFIG_DDR_DLL) 153 { 154 /* 155 * Work around to stabilize DDR DLL MSYNC_IN. 156 * Errata DDR9 seems to have been fixed. 157 * This is now the workaround for Errata DDR11: 158 * Override DLL = 1, Course Adj = 1, Tap Select = 0 159 */ 160 161 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 162 163 gur->ddrdllcr = 0x81000000; 164 asm("sync;isync;msync"); 165 udelay(200); 166 } 167 #endif 168 dram_size = spd_sdram(); 169 170 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 171 /* 172 * Initialize and enable DDR ECC. 173 */ 174 ddr_enable_ecc(dram_size); 175 #endif 176 /* 177 * SDRAM Initialization 178 */ 179 sdram_init(); 180 181 puts(" DDR: "); 182 return dram_size; 183 } 184 185 /* 186 * Initialize Local Bus 187 */ 188 void 189 local_bus_init(void) 190 { 191 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 192 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 193 194 uint clkdiv; 195 uint lbc_hz; 196 sys_info_t sysinfo; 197 198 get_sys_info(&sysinfo); 199 clkdiv = (lbc->lcrr & 0x0f) * 2; 200 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 201 202 gur->lbiuiplldcr1 = 0x00078080; 203 if (clkdiv == 16) { 204 gur->lbiuiplldcr0 = 0x7c0f1bf0; 205 } else if (clkdiv == 8) { 206 gur->lbiuiplldcr0 = 0x6c0f1bf0; 207 } else if (clkdiv == 4) { 208 gur->lbiuiplldcr0 = 0x5c0f1bf0; 209 } 210 211 lbc->lcrr |= 0x00030000; 212 213 asm("sync;isync;msync"); 214 } 215 216 /* 217 * Initialize SDRAM memory on the Local Bus. 218 */ 219 void 220 sdram_init(void) 221 { 222 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) 223 224 uint idx; 225 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 226 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 227 uint lsdmr_common; 228 229 puts(" SDRAM: "); 230 231 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 232 233 /* 234 * Setup SDRAM Base and Option Registers 235 */ 236 lbc->or2 = CFG_OR2_PRELIM; 237 asm("msync"); 238 239 lbc->br2 = CFG_BR2_PRELIM; 240 asm("msync"); 241 242 lbc->lbcr = CFG_LBC_LBCR; 243 asm("msync"); 244 245 246 lbc->lsrt = CFG_LBC_LSRT; 247 lbc->mrtpr = CFG_LBC_MRTPR; 248 asm("msync"); 249 250 /* 251 * MPC8568 uses "new" 15-16 style addressing. 252 */ 253 lsdmr_common = CFG_LBC_LSDMR_COMMON; 254 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; 255 256 /* 257 * Issue PRECHARGE ALL command. 258 */ 259 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; 260 asm("sync;msync"); 261 *sdram_addr = 0xff; 262 ppcDcbf((unsigned long) sdram_addr); 263 udelay(100); 264 265 /* 266 * Issue 8 AUTO REFRESH commands. 267 */ 268 for (idx = 0; idx < 8; idx++) { 269 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; 270 asm("sync;msync"); 271 *sdram_addr = 0xff; 272 ppcDcbf((unsigned long) sdram_addr); 273 udelay(100); 274 } 275 276 /* 277 * Issue 8 MODE-set command. 278 */ 279 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; 280 asm("sync;msync"); 281 *sdram_addr = 0xff; 282 ppcDcbf((unsigned long) sdram_addr); 283 udelay(100); 284 285 /* 286 * Issue NORMAL OP command. 287 */ 288 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; 289 asm("sync;msync"); 290 *sdram_addr = 0xff; 291 ppcDcbf((unsigned long) sdram_addr); 292 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 293 294 #endif /* enable SDRAM init */ 295 } 296 297 #if defined(CFG_DRAM_TEST) 298 int 299 testdram(void) 300 { 301 uint *pstart = (uint *) CFG_MEMTEST_START; 302 uint *pend = (uint *) CFG_MEMTEST_END; 303 uint *p; 304 305 printf("Testing DRAM from 0x%08x to 0x%08x\n", 306 CFG_MEMTEST_START, 307 CFG_MEMTEST_END); 308 309 printf("DRAM test phase 1:\n"); 310 for (p = pstart; p < pend; p++) 311 *p = 0xaaaaaaaa; 312 313 for (p = pstart; p < pend; p++) { 314 if (*p != 0xaaaaaaaa) { 315 printf ("DRAM test fails at: %08x\n", (uint) p); 316 return 1; 317 } 318 } 319 320 printf("DRAM test phase 2:\n"); 321 for (p = pstart; p < pend; p++) 322 *p = 0x55555555; 323 324 for (p = pstart; p < pend; p++) { 325 if (*p != 0x55555555) { 326 printf ("DRAM test fails at: %08x\n", (uint) p); 327 return 1; 328 } 329 } 330 331 printf("DRAM test passed.\n"); 332 return 0; 333 } 334 #endif 335 336 #if defined(CONFIG_PCI) 337 #ifndef CONFIG_PCI_PNP 338 static struct pci_config_table pci_mpc8568mds_config_table[] = { 339 { 340 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 341 pci_cfgfunc_config_device, 342 {PCI_ENET0_IOADDR, 343 PCI_ENET0_MEMADDR, 344 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} 345 }, 346 {} 347 }; 348 #endif 349 350 static struct pci_controller pci1_hose = { 351 #ifndef CONFIG_PCI_PNP 352 config_table: pci_mpc8568mds_config_table, 353 #endif 354 }; 355 #endif /* CONFIG_PCI */ 356 357 #ifdef CONFIG_PCIE1 358 static struct pci_controller pcie1_hose; 359 #endif /* CONFIG_PCIE1 */ 360 361 int first_free_busno = 0; 362 363 /* 364 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board 365 */ 366 void 367 pib_init(void) 368 { 369 u8 val8, orig_i2c_bus; 370 /* 371 * Assign PIB PMC2/3 to PCI bus 372 */ 373 374 /*switch temporarily to I2C bus #2 */ 375 orig_i2c_bus = i2c_get_bus_num(); 376 i2c_set_bus_num(1); 377 378 val8 = 0x00; 379 i2c_write(0x23, 0x6, 1, &val8, 1); 380 i2c_write(0x23, 0x7, 1, &val8, 1); 381 val8 = 0xff; 382 i2c_write(0x23, 0x2, 1, &val8, 1); 383 i2c_write(0x23, 0x3, 1, &val8, 1); 384 385 val8 = 0x00; 386 i2c_write(0x26, 0x6, 1, &val8, 1); 387 val8 = 0x34; 388 i2c_write(0x26, 0x7, 1, &val8, 1); 389 val8 = 0xf9; 390 i2c_write(0x26, 0x2, 1, &val8, 1); 391 val8 = 0xff; 392 i2c_write(0x26, 0x3, 1, &val8, 1); 393 394 val8 = 0x00; 395 i2c_write(0x27, 0x6, 1, &val8, 1); 396 i2c_write(0x27, 0x7, 1, &val8, 1); 397 val8 = 0xff; 398 i2c_write(0x27, 0x2, 1, &val8, 1); 399 val8 = 0xef; 400 i2c_write(0x27, 0x3, 1, &val8, 1); 401 402 asm("eieio"); 403 } 404 405 #ifdef CONFIG_PCI 406 void 407 pci_init_board(void) 408 { 409 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 410 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 411 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 412 413 #ifdef CONFIG_PCI1 414 { 415 pib_init(); 416 417 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 418 extern void fsl_pci_init(struct pci_controller *hose); 419 struct pci_controller *hose = &pci1_hose; 420 421 uint pci_32 = 1; /* PORDEVSR[15] */ 422 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 423 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 424 425 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); 426 427 uint pci_speed = 66666000; 428 429 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 430 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", 431 (pci_32) ? 32 : 64, 432 (pci_speed == 33333000) ? "33" : 433 (pci_speed == 66666000) ? "66" : "unknown", 434 pci_clk_sel ? "sync" : "async", 435 pci_agent ? "agent" : "host", 436 pci_arb ? "arbiter" : "external-arbiter" 437 ); 438 439 /* inbound */ 440 pci_set_region(hose->regions + 0, 441 CFG_PCI_MEMORY_BUS, 442 CFG_PCI_MEMORY_PHYS, 443 CFG_PCI_MEMORY_SIZE, 444 PCI_REGION_MEM | PCI_REGION_MEMORY); 445 446 /* outbound memory */ 447 pci_set_region(hose->regions + 1, 448 CFG_PCI1_MEM_BASE, 449 CFG_PCI1_MEM_PHYS, 450 CFG_PCI1_MEM_SIZE, 451 PCI_REGION_MEM); 452 453 /* outbound io */ 454 pci_set_region(hose->regions + 2, 455 CFG_PCI1_IO_BASE, 456 CFG_PCI1_IO_PHYS, 457 CFG_PCI1_IO_SIZE, 458 PCI_REGION_IO); 459 460 hose->region_count = 3; 461 462 hose->first_busno = first_free_busno; 463 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 464 465 fsl_pci_init(hose); 466 first_free_busno = hose->last_busno+1; 467 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 468 } else { 469 printf (" PCI: disabled\n"); 470 } 471 } 472 #else 473 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 474 #endif 475 476 #ifdef CONFIG_PCIE1 477 { 478 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 479 extern void fsl_pci_init(struct pci_controller *hose); 480 struct pci_controller *hose = &pcie1_hose; 481 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 482 483 int pcie_configured = io_sel >= 1; 484 485 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 486 printf ("\n PCIE connected to slot as %s (base address %x)", 487 pcie_ep ? "End Point" : "Root Complex", 488 (uint)pci); 489 490 if (pci->pme_msg_det) { 491 pci->pme_msg_det = 0xffffffff; 492 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 493 } 494 printf ("\n"); 495 496 /* inbound */ 497 pci_set_region(hose->regions + 0, 498 CFG_PCI_MEMORY_BUS, 499 CFG_PCI_MEMORY_PHYS, 500 CFG_PCI_MEMORY_SIZE, 501 PCI_REGION_MEM | PCI_REGION_MEMORY); 502 503 /* outbound memory */ 504 pci_set_region(hose->regions + 1, 505 CFG_PCIE1_MEM_BASE, 506 CFG_PCIE1_MEM_PHYS, 507 CFG_PCIE1_MEM_SIZE, 508 PCI_REGION_MEM); 509 510 /* outbound io */ 511 pci_set_region(hose->regions + 2, 512 CFG_PCIE1_IO_BASE, 513 CFG_PCIE1_IO_PHYS, 514 CFG_PCIE1_IO_SIZE, 515 PCI_REGION_IO); 516 517 hose->region_count = 3; 518 519 hose->first_busno=first_free_busno; 520 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 521 522 fsl_pci_init(hose); 523 printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 524 525 first_free_busno=hose->last_busno+1; 526 527 } else { 528 printf (" PCIE: disabled\n"); 529 } 530 } 531 #else 532 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 533 #endif 534 } 535 #endif /* CONFIG_PCI */ 536 537 #if defined(CONFIG_OF_BOARD_SETUP) 538 void 539 ft_board_setup(void *blob, bd_t *bd) 540 { 541 int node, tmp[2]; 542 const char *path; 543 544 ft_cpu_setup(blob, bd); 545 546 node = fdt_path_offset(blob, "/aliases"); 547 tmp[0] = 0; 548 if (node >= 0) { 549 #ifdef CONFIG_PCI1 550 path = fdt_getprop(blob, node, "pci0", NULL); 551 if (path) { 552 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 553 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 554 } 555 #endif 556 #ifdef CONFIG_PCIE1 557 path = fdt_getprop(blob, node, "pci1", NULL); 558 if (path) { 559 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 560 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 561 } 562 #endif 563 } 564 } 565 #endif 566