1acbca876SKumar Gala /* 2b092072eSZhao Chenhui * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. 3acbca876SKumar Gala * 4acbca876SKumar Gala * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5acbca876SKumar Gala * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7acbca876SKumar Gala */ 8acbca876SKumar Gala 9acbca876SKumar Gala #include <common.h> 10acbca876SKumar Gala #include <pci.h> 11acbca876SKumar Gala #include <asm/processor.h> 12e6f5b35bSJon Loeliger #include <asm/mmu.h> 13acbca876SKumar Gala #include <asm/immap_85xx.h> 14c8514622SKumar Gala #include <asm/fsl_pci.h> 155614e71bSYork Sun #include <fsl_ddr_sdram.h> 165d27e02cSKumar Gala #include <asm/fsl_serdes.h> 17a30a549aSJon Loeliger #include <spd_sdram.h> 18acbca876SKumar Gala #include <i2c.h> 19acbca876SKumar Gala #include <ioports.h> 20acbca876SKumar Gala #include <libfdt.h> 21acbca876SKumar Gala #include <fdt_support.h> 22acbca876SKumar Gala 23acbca876SKumar Gala #include "bcsr.h" 24acbca876SKumar Gala 25acbca876SKumar Gala const qe_iop_conf_t qe_iop_conf_tab[] = { 26acbca876SKumar Gala /* GETH1 */ 27acbca876SKumar Gala {4, 10, 1, 0, 2}, /* TxD0 */ 28acbca876SKumar Gala {4, 9, 1, 0, 2}, /* TxD1 */ 29acbca876SKumar Gala {4, 8, 1, 0, 2}, /* TxD2 */ 30acbca876SKumar Gala {4, 7, 1, 0, 2}, /* TxD3 */ 31acbca876SKumar Gala {4, 23, 1, 0, 2}, /* TxD4 */ 32acbca876SKumar Gala {4, 22, 1, 0, 2}, /* TxD5 */ 33acbca876SKumar Gala {4, 21, 1, 0, 2}, /* TxD6 */ 34acbca876SKumar Gala {4, 20, 1, 0, 2}, /* TxD7 */ 35acbca876SKumar Gala {4, 15, 2, 0, 2}, /* RxD0 */ 36acbca876SKumar Gala {4, 14, 2, 0, 2}, /* RxD1 */ 37acbca876SKumar Gala {4, 13, 2, 0, 2}, /* RxD2 */ 38acbca876SKumar Gala {4, 12, 2, 0, 2}, /* RxD3 */ 39acbca876SKumar Gala {4, 29, 2, 0, 2}, /* RxD4 */ 40acbca876SKumar Gala {4, 28, 2, 0, 2}, /* RxD5 */ 41acbca876SKumar Gala {4, 27, 2, 0, 2}, /* RxD6 */ 42acbca876SKumar Gala {4, 26, 2, 0, 2}, /* RxD7 */ 43acbca876SKumar Gala {4, 11, 1, 0, 2}, /* TX_EN */ 44acbca876SKumar Gala {4, 24, 1, 0, 2}, /* TX_ER */ 45acbca876SKumar Gala {4, 16, 2, 0, 2}, /* RX_DV */ 46acbca876SKumar Gala {4, 30, 2, 0, 2}, /* RX_ER */ 47acbca876SKumar Gala {4, 17, 2, 0, 2}, /* RX_CLK */ 48acbca876SKumar Gala {4, 19, 1, 0, 2}, /* GTX_CLK */ 49acbca876SKumar Gala {1, 31, 2, 0, 3}, /* GTX125 */ 50acbca876SKumar Gala 51acbca876SKumar Gala /* GETH2 */ 52acbca876SKumar Gala {5, 10, 1, 0, 2}, /* TxD0 */ 53acbca876SKumar Gala {5, 9, 1, 0, 2}, /* TxD1 */ 54acbca876SKumar Gala {5, 8, 1, 0, 2}, /* TxD2 */ 55acbca876SKumar Gala {5, 7, 1, 0, 2}, /* TxD3 */ 56acbca876SKumar Gala {5, 23, 1, 0, 2}, /* TxD4 */ 57acbca876SKumar Gala {5, 22, 1, 0, 2}, /* TxD5 */ 58acbca876SKumar Gala {5, 21, 1, 0, 2}, /* TxD6 */ 59acbca876SKumar Gala {5, 20, 1, 0, 2}, /* TxD7 */ 60acbca876SKumar Gala {5, 15, 2, 0, 2}, /* RxD0 */ 61acbca876SKumar Gala {5, 14, 2, 0, 2}, /* RxD1 */ 62acbca876SKumar Gala {5, 13, 2, 0, 2}, /* RxD2 */ 63acbca876SKumar Gala {5, 12, 2, 0, 2}, /* RxD3 */ 64acbca876SKumar Gala {5, 29, 2, 0, 2}, /* RxD4 */ 65acbca876SKumar Gala {5, 28, 2, 0, 2}, /* RxD5 */ 66acbca876SKumar Gala {5, 27, 2, 0, 3}, /* RxD6 */ 67acbca876SKumar Gala {5, 26, 2, 0, 2}, /* RxD7 */ 68acbca876SKumar Gala {5, 11, 1, 0, 2}, /* TX_EN */ 69acbca876SKumar Gala {5, 24, 1, 0, 2}, /* TX_ER */ 70acbca876SKumar Gala {5, 16, 2, 0, 2}, /* RX_DV */ 71acbca876SKumar Gala {5, 30, 2, 0, 2}, /* RX_ER */ 72acbca876SKumar Gala {5, 17, 2, 0, 2}, /* RX_CLK */ 73acbca876SKumar Gala {5, 19, 1, 0, 2}, /* GTX_CLK */ 74acbca876SKumar Gala {1, 31, 2, 0, 3}, /* GTX125 */ 75acbca876SKumar Gala {4, 6, 3, 0, 2}, /* MDIO */ 76acbca876SKumar Gala {4, 5, 1, 0, 2}, /* MDC */ 7764d4bcb0SAnton Vorontsov 7864d4bcb0SAnton Vorontsov /* UART1 */ 7964d4bcb0SAnton Vorontsov {2, 0, 1, 0, 2}, /* UART_SOUT1 */ 8064d4bcb0SAnton Vorontsov {2, 1, 1, 0, 2}, /* UART_RTS1 */ 8164d4bcb0SAnton Vorontsov {2, 2, 2, 0, 2}, /* UART_CTS1 */ 8264d4bcb0SAnton Vorontsov {2, 3, 2, 0, 2}, /* UART_SIN1 */ 8364d4bcb0SAnton Vorontsov 84acbca876SKumar Gala {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 85acbca876SKumar Gala }; 86acbca876SKumar Gala 87acbca876SKumar Gala void local_bus_init(void); 88acbca876SKumar Gala 89acbca876SKumar Gala int board_early_init_f (void) 90acbca876SKumar Gala { 91acbca876SKumar Gala /* 92acbca876SKumar Gala * Initialize local bus. 93acbca876SKumar Gala */ 94acbca876SKumar Gala local_bus_init (); 95acbca876SKumar Gala 96acbca876SKumar Gala enable_8568mds_duart(); 97acbca876SKumar Gala enable_8568mds_flash_write(); 98ad162249SAnton Vorontsov #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 99ad162249SAnton Vorontsov reset_8568mds_uccs(); 100ad162249SAnton Vorontsov #endif 101acbca876SKumar Gala #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) 102acbca876SKumar Gala enable_8568mds_qe_mdio(); 103acbca876SKumar Gala #endif 104acbca876SKumar Gala 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_I2C2_OFFSET 106acbca876SKumar Gala /* Enable I2C2_SCL and I2C2_SDA */ 107acbca876SKumar Gala volatile struct par_io *port_c; 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140); 109acbca876SKumar Gala port_c->cpdir2 |= 0x0f000000; 110acbca876SKumar Gala port_c->cppar2 &= ~0x0f000000; 111acbca876SKumar Gala port_c->cppar2 |= 0x0a000000; 112acbca876SKumar Gala #endif 113acbca876SKumar Gala 114acbca876SKumar Gala return 0; 115acbca876SKumar Gala } 116acbca876SKumar Gala 117acbca876SKumar Gala int checkboard (void) 118acbca876SKumar Gala { 119acbca876SKumar Gala printf ("Board: 8568 MDS\n"); 120acbca876SKumar Gala 121acbca876SKumar Gala return 0; 122acbca876SKumar Gala } 123acbca876SKumar Gala 124acbca876SKumar Gala /* 125acbca876SKumar Gala * Initialize Local Bus 126acbca876SKumar Gala */ 127acbca876SKumar Gala void 128acbca876SKumar Gala local_bus_init(void) 129acbca876SKumar Gala { 1306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 131f51cdaf1SBecky Bruce volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 132acbca876SKumar Gala 133acbca876SKumar Gala uint clkdiv; 134acbca876SKumar Gala sys_info_t sysinfo; 135acbca876SKumar Gala 136acbca876SKumar Gala get_sys_info(&sysinfo); 137a5d212a2STrent Piepho clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 138acbca876SKumar Gala 139acbca876SKumar Gala gur->lbiuiplldcr1 = 0x00078080; 140acbca876SKumar Gala if (clkdiv == 16) { 141acbca876SKumar Gala gur->lbiuiplldcr0 = 0x7c0f1bf0; 142acbca876SKumar Gala } else if (clkdiv == 8) { 143acbca876SKumar Gala gur->lbiuiplldcr0 = 0x6c0f1bf0; 144acbca876SKumar Gala } else if (clkdiv == 4) { 145acbca876SKumar Gala gur->lbiuiplldcr0 = 0x5c0f1bf0; 146acbca876SKumar Gala } 147acbca876SKumar Gala 148acbca876SKumar Gala lbc->lcrr |= 0x00030000; 149acbca876SKumar Gala 150acbca876SKumar Gala asm("sync;isync;msync"); 151acbca876SKumar Gala } 152acbca876SKumar Gala 153acbca876SKumar Gala /* 154acbca876SKumar Gala * Initialize SDRAM memory on the Local Bus. 155acbca876SKumar Gala */ 15670961ba4SBecky Bruce void lbc_sdram_init(void) 157acbca876SKumar Gala { 1586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 159acbca876SKumar Gala 160acbca876SKumar Gala uint idx; 161f51cdaf1SBecky Bruce volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 1626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 163acbca876SKumar Gala uint lsdmr_common; 164acbca876SKumar Gala 1657ea3871eSBecky Bruce puts("LBC SDRAM: "); 1667ea3871eSBecky Bruce print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, 1677ea3871eSBecky Bruce "\n "); 168acbca876SKumar Gala 169acbca876SKumar Gala /* 170acbca876SKumar Gala * Setup SDRAM Base and Option Registers 171acbca876SKumar Gala */ 172f51cdaf1SBecky Bruce set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 173f51cdaf1SBecky Bruce set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 174acbca876SKumar Gala asm("msync"); 175acbca876SKumar Gala 1766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lbcr = CONFIG_SYS_LBC_LBCR; 177acbca876SKumar Gala asm("msync"); 178acbca876SKumar Gala 1796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lsrt = CONFIG_SYS_LBC_LSRT; 1806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 181acbca876SKumar Gala asm("msync"); 182acbca876SKumar Gala 183acbca876SKumar Gala /* 184acbca876SKumar Gala * MPC8568 uses "new" 15-16 style addressing. 185acbca876SKumar Gala */ 1866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 187b0fe93edSKumar Gala lsdmr_common |= LSDMR_BSMA1516; 188acbca876SKumar Gala 189acbca876SKumar Gala /* 190acbca876SKumar Gala * Issue PRECHARGE ALL command. 191acbca876SKumar Gala */ 192b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 193acbca876SKumar Gala asm("sync;msync"); 194acbca876SKumar Gala *sdram_addr = 0xff; 195acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 196acbca876SKumar Gala udelay(100); 197acbca876SKumar Gala 198acbca876SKumar Gala /* 199acbca876SKumar Gala * Issue 8 AUTO REFRESH commands. 200acbca876SKumar Gala */ 201acbca876SKumar Gala for (idx = 0; idx < 8; idx++) { 202b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 203acbca876SKumar Gala asm("sync;msync"); 204acbca876SKumar Gala *sdram_addr = 0xff; 205acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 206acbca876SKumar Gala udelay(100); 207acbca876SKumar Gala } 208acbca876SKumar Gala 209acbca876SKumar Gala /* 210acbca876SKumar Gala * Issue 8 MODE-set command. 211acbca876SKumar Gala */ 212b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 213acbca876SKumar Gala asm("sync;msync"); 214acbca876SKumar Gala *sdram_addr = 0xff; 215acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 216acbca876SKumar Gala udelay(100); 217acbca876SKumar Gala 218acbca876SKumar Gala /* 219acbca876SKumar Gala * Issue NORMAL OP command. 220acbca876SKumar Gala */ 221b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 222acbca876SKumar Gala asm("sync;msync"); 223acbca876SKumar Gala *sdram_addr = 0xff; 224acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 225acbca876SKumar Gala udelay(200); /* Overkill. Must wait > 200 bus cycles */ 226acbca876SKumar Gala 227acbca876SKumar Gala #endif /* enable SDRAM init */ 228acbca876SKumar Gala } 229acbca876SKumar Gala 230acbca876SKumar Gala #if defined(CONFIG_PCI) 231acbca876SKumar Gala #ifndef CONFIG_PCI_PNP 232acbca876SKumar Gala static struct pci_config_table pci_mpc8568mds_config_table[] = { 233acbca876SKumar Gala { 234acbca876SKumar Gala PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 235acbca876SKumar Gala pci_cfgfunc_config_device, 236acbca876SKumar Gala {PCI_ENET0_IOADDR, 237acbca876SKumar Gala PCI_ENET0_MEMADDR, 238acbca876SKumar Gala PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} 239acbca876SKumar Gala }, 240acbca876SKumar Gala {} 241acbca876SKumar Gala }; 242acbca876SKumar Gala #endif 243acbca876SKumar Gala 244b092072eSZhao Chenhui static struct pci_controller pci1_hose; 245acbca876SKumar Gala #endif /* CONFIG_PCI */ 246acbca876SKumar Gala 247acbca876SKumar Gala /* 248acbca876SKumar Gala * pib_init() -- Initialize the PCA9555 IO expander on the PIB board 249acbca876SKumar Gala */ 250acbca876SKumar Gala void 251acbca876SKumar Gala pib_init(void) 252acbca876SKumar Gala { 253acbca876SKumar Gala u8 val8, orig_i2c_bus; 254acbca876SKumar Gala /* 255acbca876SKumar Gala * Assign PIB PMC2/3 to PCI bus 256acbca876SKumar Gala */ 257acbca876SKumar Gala 258acbca876SKumar Gala /*switch temporarily to I2C bus #2 */ 259acbca876SKumar Gala orig_i2c_bus = i2c_get_bus_num(); 260acbca876SKumar Gala i2c_set_bus_num(1); 261acbca876SKumar Gala 262acbca876SKumar Gala val8 = 0x00; 263acbca876SKumar Gala i2c_write(0x23, 0x6, 1, &val8, 1); 264acbca876SKumar Gala i2c_write(0x23, 0x7, 1, &val8, 1); 265acbca876SKumar Gala val8 = 0xff; 266acbca876SKumar Gala i2c_write(0x23, 0x2, 1, &val8, 1); 267acbca876SKumar Gala i2c_write(0x23, 0x3, 1, &val8, 1); 268acbca876SKumar Gala 269acbca876SKumar Gala val8 = 0x00; 270acbca876SKumar Gala i2c_write(0x26, 0x6, 1, &val8, 1); 271acbca876SKumar Gala val8 = 0x34; 272acbca876SKumar Gala i2c_write(0x26, 0x7, 1, &val8, 1); 273acbca876SKumar Gala val8 = 0xf9; 274acbca876SKumar Gala i2c_write(0x26, 0x2, 1, &val8, 1); 275acbca876SKumar Gala val8 = 0xff; 276acbca876SKumar Gala i2c_write(0x26, 0x3, 1, &val8, 1); 277acbca876SKumar Gala 278acbca876SKumar Gala val8 = 0x00; 279acbca876SKumar Gala i2c_write(0x27, 0x6, 1, &val8, 1); 280acbca876SKumar Gala i2c_write(0x27, 0x7, 1, &val8, 1); 281acbca876SKumar Gala val8 = 0xff; 282acbca876SKumar Gala i2c_write(0x27, 0x2, 1, &val8, 1); 283acbca876SKumar Gala val8 = 0xef; 284acbca876SKumar Gala i2c_write(0x27, 0x3, 1, &val8, 1); 285acbca876SKumar Gala 286acbca876SKumar Gala asm("eieio"); 287502dd36bSKumar Gala i2c_set_bus_num(orig_i2c_bus); 288acbca876SKumar Gala } 289acbca876SKumar Gala 290acbca876SKumar Gala #ifdef CONFIG_PCI 2914681457eSKumar Gala void pci_init_board(void) 292acbca876SKumar Gala { 2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 2943f6f9d76SKumar Gala int first_free_busno = 0; 2953f6f9d76SKumar Gala #ifdef CONFIG_PCI1 2963f6f9d76SKumar Gala struct fsl_pci_info pci_info; 2974681457eSKumar Gala u32 devdisr, pordevsr, io_sel; 2984681457eSKumar Gala u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 2994681457eSKumar Gala 3004681457eSKumar Gala devdisr = in_be32(&gur->devdisr); 3014681457eSKumar Gala pordevsr = in_be32(&gur->pordevsr); 3024681457eSKumar Gala porpllsr = in_be32(&gur->porpllsr); 3034681457eSKumar Gala io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 3044681457eSKumar Gala 3054681457eSKumar Gala debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 306acbca876SKumar Gala 3074681457eSKumar Gala pci_speed = 66666000; 3084681457eSKumar Gala pci_32 = 1; 3094681457eSKumar Gala pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 3104681457eSKumar Gala pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 311acbca876SKumar Gala 3124681457eSKumar Gala if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 3133f6f9d76SKumar Gala SET_STD_PCI_INFO(pci_info, 1); 3143f6f9d76SKumar Gala set_next_law(pci_info.mem_phys, 3153f6f9d76SKumar Gala law_size_bits(pci_info.mem_size), pci_info.law); 3163f6f9d76SKumar Gala set_next_law(pci_info.io_phys, 3173f6f9d76SKumar Gala law_size_bits(pci_info.io_size), pci_info.law); 3183f6f9d76SKumar Gala 3193f6f9d76SKumar Gala pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 3208ca78f2cSPeter Tyser printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 321acbca876SKumar Gala (pci_32) ? 32 : 64, 322acbca876SKumar Gala (pci_speed == 33333000) ? "33" : 323acbca876SKumar Gala (pci_speed == 66666000) ? "66" : "unknown", 324acbca876SKumar Gala pci_clk_sel ? "sync" : "async", 325acbca876SKumar Gala pci_agent ? "agent" : "host", 3264681457eSKumar Gala pci_arb ? "arbiter" : "external-arbiter", 3273f6f9d76SKumar Gala pci_info.regs); 328acbca876SKumar Gala 329b092072eSZhao Chenhui #ifndef CONFIG_PCI_PNP 330b092072eSZhao Chenhui pci1_hose.config_table = pci_mpc8568mds_config_table; 331b092072eSZhao Chenhui #endif 3323f6f9d76SKumar Gala first_free_busno = fsl_pci_init_port(&pci_info, 3334681457eSKumar Gala &pci1_hose, first_free_busno); 334acbca876SKumar Gala } else { 335acbca876SKumar Gala printf("PCI: disabled\n"); 336acbca876SKumar Gala } 3374681457eSKumar Gala 3384681457eSKumar Gala puts("\n"); 339acbca876SKumar Gala #else 3404681457eSKumar Gala setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 341acbca876SKumar Gala #endif 342acbca876SKumar Gala 3433f6f9d76SKumar Gala fsl_pcie_init_board(first_free_busno); 344acbca876SKumar Gala } 345acbca876SKumar Gala #endif /* CONFIG_PCI */ 346acbca876SKumar Gala 347acbca876SKumar Gala #if defined(CONFIG_OF_BOARD_SETUP) 348*e895a4b0SSimon Glass int ft_board_setup(void *blob, bd_t *bd) 3492dba0deaSKumar Gala { 350acbca876SKumar Gala ft_cpu_setup(blob, bd); 351acbca876SKumar Gala 3526525d51fSKumar Gala FT_FSL_PCI_SETUP; 353*e895a4b0SSimon Glass 354*e895a4b0SSimon Glass return 0; 355acbca876SKumar Gala } 356acbca876SKumar Gala #endif 357