1acbca876SKumar Gala /* 2acbca876SKumar Gala * Copyright 2007 Freescale Semiconductor. 3acbca876SKumar Gala * 4acbca876SKumar Gala * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5acbca876SKumar Gala * 6acbca876SKumar Gala * See file CREDITS for list of people who contributed to this 7acbca876SKumar Gala * project. 8acbca876SKumar Gala * 9acbca876SKumar Gala * This program is free software; you can redistribute it and/or 10acbca876SKumar Gala * modify it under the terms of the GNU General Public License as 11acbca876SKumar Gala * published by the Free Software Foundation; either version 2 of 12acbca876SKumar Gala * the License, or (at your option) any later version. 13acbca876SKumar Gala * 14acbca876SKumar Gala * This program is distributed in the hope that it will be useful, 15acbca876SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 16acbca876SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17acbca876SKumar Gala * GNU General Public License for more details. 18acbca876SKumar Gala * 19acbca876SKumar Gala * You should have received a copy of the GNU General Public License 20acbca876SKumar Gala * along with this program; if not, write to the Free Software 21acbca876SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22acbca876SKumar Gala * MA 02111-1307 USA 23acbca876SKumar Gala */ 24acbca876SKumar Gala 25acbca876SKumar Gala #include <common.h> 26acbca876SKumar Gala #include <pci.h> 27acbca876SKumar Gala #include <asm/processor.h> 28*e6f5b35bSJon Loeliger #include <asm/mmu.h> 29acbca876SKumar Gala #include <asm/immap_85xx.h> 30acbca876SKumar Gala #include <asm/immap_fsl_pci.h> 31*e6f5b35bSJon Loeliger #include <asm/fsl_ddr_sdram.h> 32a30a549aSJon Loeliger #include <spd_sdram.h> 33acbca876SKumar Gala #include <i2c.h> 34acbca876SKumar Gala #include <ioports.h> 35acbca876SKumar Gala #include <libfdt.h> 36acbca876SKumar Gala #include <fdt_support.h> 37acbca876SKumar Gala 38acbca876SKumar Gala #include "bcsr.h" 39acbca876SKumar Gala 40acbca876SKumar Gala const qe_iop_conf_t qe_iop_conf_tab[] = { 41acbca876SKumar Gala /* GETH1 */ 42acbca876SKumar Gala {4, 10, 1, 0, 2}, /* TxD0 */ 43acbca876SKumar Gala {4, 9, 1, 0, 2}, /* TxD1 */ 44acbca876SKumar Gala {4, 8, 1, 0, 2}, /* TxD2 */ 45acbca876SKumar Gala {4, 7, 1, 0, 2}, /* TxD3 */ 46acbca876SKumar Gala {4, 23, 1, 0, 2}, /* TxD4 */ 47acbca876SKumar Gala {4, 22, 1, 0, 2}, /* TxD5 */ 48acbca876SKumar Gala {4, 21, 1, 0, 2}, /* TxD6 */ 49acbca876SKumar Gala {4, 20, 1, 0, 2}, /* TxD7 */ 50acbca876SKumar Gala {4, 15, 2, 0, 2}, /* RxD0 */ 51acbca876SKumar Gala {4, 14, 2, 0, 2}, /* RxD1 */ 52acbca876SKumar Gala {4, 13, 2, 0, 2}, /* RxD2 */ 53acbca876SKumar Gala {4, 12, 2, 0, 2}, /* RxD3 */ 54acbca876SKumar Gala {4, 29, 2, 0, 2}, /* RxD4 */ 55acbca876SKumar Gala {4, 28, 2, 0, 2}, /* RxD5 */ 56acbca876SKumar Gala {4, 27, 2, 0, 2}, /* RxD6 */ 57acbca876SKumar Gala {4, 26, 2, 0, 2}, /* RxD7 */ 58acbca876SKumar Gala {4, 11, 1, 0, 2}, /* TX_EN */ 59acbca876SKumar Gala {4, 24, 1, 0, 2}, /* TX_ER */ 60acbca876SKumar Gala {4, 16, 2, 0, 2}, /* RX_DV */ 61acbca876SKumar Gala {4, 30, 2, 0, 2}, /* RX_ER */ 62acbca876SKumar Gala {4, 17, 2, 0, 2}, /* RX_CLK */ 63acbca876SKumar Gala {4, 19, 1, 0, 2}, /* GTX_CLK */ 64acbca876SKumar Gala {1, 31, 2, 0, 3}, /* GTX125 */ 65acbca876SKumar Gala 66acbca876SKumar Gala /* GETH2 */ 67acbca876SKumar Gala {5, 10, 1, 0, 2}, /* TxD0 */ 68acbca876SKumar Gala {5, 9, 1, 0, 2}, /* TxD1 */ 69acbca876SKumar Gala {5, 8, 1, 0, 2}, /* TxD2 */ 70acbca876SKumar Gala {5, 7, 1, 0, 2}, /* TxD3 */ 71acbca876SKumar Gala {5, 23, 1, 0, 2}, /* TxD4 */ 72acbca876SKumar Gala {5, 22, 1, 0, 2}, /* TxD5 */ 73acbca876SKumar Gala {5, 21, 1, 0, 2}, /* TxD6 */ 74acbca876SKumar Gala {5, 20, 1, 0, 2}, /* TxD7 */ 75acbca876SKumar Gala {5, 15, 2, 0, 2}, /* RxD0 */ 76acbca876SKumar Gala {5, 14, 2, 0, 2}, /* RxD1 */ 77acbca876SKumar Gala {5, 13, 2, 0, 2}, /* RxD2 */ 78acbca876SKumar Gala {5, 12, 2, 0, 2}, /* RxD3 */ 79acbca876SKumar Gala {5, 29, 2, 0, 2}, /* RxD4 */ 80acbca876SKumar Gala {5, 28, 2, 0, 2}, /* RxD5 */ 81acbca876SKumar Gala {5, 27, 2, 0, 3}, /* RxD6 */ 82acbca876SKumar Gala {5, 26, 2, 0, 2}, /* RxD7 */ 83acbca876SKumar Gala {5, 11, 1, 0, 2}, /* TX_EN */ 84acbca876SKumar Gala {5, 24, 1, 0, 2}, /* TX_ER */ 85acbca876SKumar Gala {5, 16, 2, 0, 2}, /* RX_DV */ 86acbca876SKumar Gala {5, 30, 2, 0, 2}, /* RX_ER */ 87acbca876SKumar Gala {5, 17, 2, 0, 2}, /* RX_CLK */ 88acbca876SKumar Gala {5, 19, 1, 0, 2}, /* GTX_CLK */ 89acbca876SKumar Gala {1, 31, 2, 0, 3}, /* GTX125 */ 90acbca876SKumar Gala {4, 6, 3, 0, 2}, /* MDIO */ 91acbca876SKumar Gala {4, 5, 1, 0, 2}, /* MDC */ 9264d4bcb0SAnton Vorontsov 9364d4bcb0SAnton Vorontsov /* UART1 */ 9464d4bcb0SAnton Vorontsov {2, 0, 1, 0, 2}, /* UART_SOUT1 */ 9564d4bcb0SAnton Vorontsov {2, 1, 1, 0, 2}, /* UART_RTS1 */ 9664d4bcb0SAnton Vorontsov {2, 2, 2, 0, 2}, /* UART_CTS1 */ 9764d4bcb0SAnton Vorontsov {2, 3, 2, 0, 2}, /* UART_SIN1 */ 9864d4bcb0SAnton Vorontsov 99acbca876SKumar Gala {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 100acbca876SKumar Gala }; 101acbca876SKumar Gala 102acbca876SKumar Gala 103acbca876SKumar Gala #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 104acbca876SKumar Gala extern void ddr_enable_ecc(unsigned int dram_size); 105acbca876SKumar Gala #endif 106acbca876SKumar Gala 107acbca876SKumar Gala void local_bus_init(void); 108acbca876SKumar Gala void sdram_init(void); 109acbca876SKumar Gala 110acbca876SKumar Gala int board_early_init_f (void) 111acbca876SKumar Gala { 112acbca876SKumar Gala /* 113acbca876SKumar Gala * Initialize local bus. 114acbca876SKumar Gala */ 115acbca876SKumar Gala local_bus_init (); 116acbca876SKumar Gala 117acbca876SKumar Gala enable_8568mds_duart(); 118acbca876SKumar Gala enable_8568mds_flash_write(); 119ad162249SAnton Vorontsov #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 120ad162249SAnton Vorontsov reset_8568mds_uccs(); 121ad162249SAnton Vorontsov #endif 122acbca876SKumar Gala #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) 123acbca876SKumar Gala enable_8568mds_qe_mdio(); 124acbca876SKumar Gala #endif 125acbca876SKumar Gala 126acbca876SKumar Gala #ifdef CFG_I2C2_OFFSET 127acbca876SKumar Gala /* Enable I2C2_SCL and I2C2_SDA */ 128acbca876SKumar Gala volatile struct par_io *port_c; 129acbca876SKumar Gala port_c = (struct par_io*)(CFG_IMMR + 0xe0140); 130acbca876SKumar Gala port_c->cpdir2 |= 0x0f000000; 131acbca876SKumar Gala port_c->cppar2 &= ~0x0f000000; 132acbca876SKumar Gala port_c->cppar2 |= 0x0a000000; 133acbca876SKumar Gala #endif 134acbca876SKumar Gala 135acbca876SKumar Gala return 0; 136acbca876SKumar Gala } 137acbca876SKumar Gala 138acbca876SKumar Gala int checkboard (void) 139acbca876SKumar Gala { 140acbca876SKumar Gala printf ("Board: 8568 MDS\n"); 141acbca876SKumar Gala 142acbca876SKumar Gala return 0; 143acbca876SKumar Gala } 144acbca876SKumar Gala 1459973e3c6SBecky Bruce phys_size_t 146acbca876SKumar Gala initdram(int board_type) 147acbca876SKumar Gala { 148acbca876SKumar Gala long dram_size = 0; 149acbca876SKumar Gala 150acbca876SKumar Gala puts("Initializing\n"); 151acbca876SKumar Gala 152acbca876SKumar Gala #if defined(CONFIG_DDR_DLL) 153acbca876SKumar Gala { 154acbca876SKumar Gala /* 155acbca876SKumar Gala * Work around to stabilize DDR DLL MSYNC_IN. 156acbca876SKumar Gala * Errata DDR9 seems to have been fixed. 157acbca876SKumar Gala * This is now the workaround for Errata DDR11: 158acbca876SKumar Gala * Override DLL = 1, Course Adj = 1, Tap Select = 0 159acbca876SKumar Gala */ 160acbca876SKumar Gala 161acbca876SKumar Gala volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 162acbca876SKumar Gala 163acbca876SKumar Gala gur->ddrdllcr = 0x81000000; 164acbca876SKumar Gala asm("sync;isync;msync"); 165acbca876SKumar Gala udelay(200); 166acbca876SKumar Gala } 167acbca876SKumar Gala #endif 168*e6f5b35bSJon Loeliger 169*e6f5b35bSJon Loeliger dram_size = fsl_ddr_sdram(); 170*e6f5b35bSJon Loeliger dram_size = setup_ddr_tlbs(dram_size / 0x100000); 171*e6f5b35bSJon Loeliger dram_size *= 0x100000; 172acbca876SKumar Gala 173acbca876SKumar Gala #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 174acbca876SKumar Gala /* 175acbca876SKumar Gala * Initialize and enable DDR ECC. 176acbca876SKumar Gala */ 177acbca876SKumar Gala ddr_enable_ecc(dram_size); 178acbca876SKumar Gala #endif 179*e6f5b35bSJon Loeliger 180acbca876SKumar Gala /* 181acbca876SKumar Gala * SDRAM Initialization 182acbca876SKumar Gala */ 183acbca876SKumar Gala sdram_init(); 184acbca876SKumar Gala 185acbca876SKumar Gala puts(" DDR: "); 186acbca876SKumar Gala return dram_size; 187acbca876SKumar Gala } 188acbca876SKumar Gala 189acbca876SKumar Gala /* 190acbca876SKumar Gala * Initialize Local Bus 191acbca876SKumar Gala */ 192acbca876SKumar Gala void 193acbca876SKumar Gala local_bus_init(void) 194acbca876SKumar Gala { 195acbca876SKumar Gala volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 196acbca876SKumar Gala volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 197acbca876SKumar Gala 198acbca876SKumar Gala uint clkdiv; 199acbca876SKumar Gala uint lbc_hz; 200acbca876SKumar Gala sys_info_t sysinfo; 201acbca876SKumar Gala 202acbca876SKumar Gala get_sys_info(&sysinfo); 203acbca876SKumar Gala clkdiv = (lbc->lcrr & 0x0f) * 2; 204acbca876SKumar Gala lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 205acbca876SKumar Gala 206acbca876SKumar Gala gur->lbiuiplldcr1 = 0x00078080; 207acbca876SKumar Gala if (clkdiv == 16) { 208acbca876SKumar Gala gur->lbiuiplldcr0 = 0x7c0f1bf0; 209acbca876SKumar Gala } else if (clkdiv == 8) { 210acbca876SKumar Gala gur->lbiuiplldcr0 = 0x6c0f1bf0; 211acbca876SKumar Gala } else if (clkdiv == 4) { 212acbca876SKumar Gala gur->lbiuiplldcr0 = 0x5c0f1bf0; 213acbca876SKumar Gala } 214acbca876SKumar Gala 215acbca876SKumar Gala lbc->lcrr |= 0x00030000; 216acbca876SKumar Gala 217acbca876SKumar Gala asm("sync;isync;msync"); 218acbca876SKumar Gala } 219acbca876SKumar Gala 220acbca876SKumar Gala /* 221acbca876SKumar Gala * Initialize SDRAM memory on the Local Bus. 222acbca876SKumar Gala */ 223acbca876SKumar Gala void 224acbca876SKumar Gala sdram_init(void) 225acbca876SKumar Gala { 226acbca876SKumar Gala #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) 227acbca876SKumar Gala 228acbca876SKumar Gala uint idx; 229acbca876SKumar Gala volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 230acbca876SKumar Gala uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 231acbca876SKumar Gala uint lsdmr_common; 232acbca876SKumar Gala 233acbca876SKumar Gala puts(" SDRAM: "); 234acbca876SKumar Gala 235acbca876SKumar Gala print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 236acbca876SKumar Gala 237acbca876SKumar Gala /* 238acbca876SKumar Gala * Setup SDRAM Base and Option Registers 239acbca876SKumar Gala */ 240acbca876SKumar Gala lbc->or2 = CFG_OR2_PRELIM; 241acbca876SKumar Gala asm("msync"); 242acbca876SKumar Gala 243acbca876SKumar Gala lbc->br2 = CFG_BR2_PRELIM; 244acbca876SKumar Gala asm("msync"); 245acbca876SKumar Gala 246acbca876SKumar Gala lbc->lbcr = CFG_LBC_LBCR; 247acbca876SKumar Gala asm("msync"); 248acbca876SKumar Gala 249acbca876SKumar Gala 250acbca876SKumar Gala lbc->lsrt = CFG_LBC_LSRT; 251acbca876SKumar Gala lbc->mrtpr = CFG_LBC_MRTPR; 252acbca876SKumar Gala asm("msync"); 253acbca876SKumar Gala 254acbca876SKumar Gala /* 255acbca876SKumar Gala * MPC8568 uses "new" 15-16 style addressing. 256acbca876SKumar Gala */ 257acbca876SKumar Gala lsdmr_common = CFG_LBC_LSDMR_COMMON; 258acbca876SKumar Gala lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; 259acbca876SKumar Gala 260acbca876SKumar Gala /* 261acbca876SKumar Gala * Issue PRECHARGE ALL command. 262acbca876SKumar Gala */ 263acbca876SKumar Gala lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; 264acbca876SKumar Gala asm("sync;msync"); 265acbca876SKumar Gala *sdram_addr = 0xff; 266acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 267acbca876SKumar Gala udelay(100); 268acbca876SKumar Gala 269acbca876SKumar Gala /* 270acbca876SKumar Gala * Issue 8 AUTO REFRESH commands. 271acbca876SKumar Gala */ 272acbca876SKumar Gala for (idx = 0; idx < 8; idx++) { 273acbca876SKumar Gala lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; 274acbca876SKumar Gala asm("sync;msync"); 275acbca876SKumar Gala *sdram_addr = 0xff; 276acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 277acbca876SKumar Gala udelay(100); 278acbca876SKumar Gala } 279acbca876SKumar Gala 280acbca876SKumar Gala /* 281acbca876SKumar Gala * Issue 8 MODE-set command. 282acbca876SKumar Gala */ 283acbca876SKumar Gala lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; 284acbca876SKumar Gala asm("sync;msync"); 285acbca876SKumar Gala *sdram_addr = 0xff; 286acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 287acbca876SKumar Gala udelay(100); 288acbca876SKumar Gala 289acbca876SKumar Gala /* 290acbca876SKumar Gala * Issue NORMAL OP command. 291acbca876SKumar Gala */ 292acbca876SKumar Gala lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; 293acbca876SKumar Gala asm("sync;msync"); 294acbca876SKumar Gala *sdram_addr = 0xff; 295acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 296acbca876SKumar Gala udelay(200); /* Overkill. Must wait > 200 bus cycles */ 297acbca876SKumar Gala 298acbca876SKumar Gala #endif /* enable SDRAM init */ 299acbca876SKumar Gala } 300acbca876SKumar Gala 301acbca876SKumar Gala #if defined(CONFIG_PCI) 302acbca876SKumar Gala #ifndef CONFIG_PCI_PNP 303acbca876SKumar Gala static struct pci_config_table pci_mpc8568mds_config_table[] = { 304acbca876SKumar Gala { 305acbca876SKumar Gala PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 306acbca876SKumar Gala pci_cfgfunc_config_device, 307acbca876SKumar Gala {PCI_ENET0_IOADDR, 308acbca876SKumar Gala PCI_ENET0_MEMADDR, 309acbca876SKumar Gala PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} 310acbca876SKumar Gala }, 311acbca876SKumar Gala {} 312acbca876SKumar Gala }; 313acbca876SKumar Gala #endif 314acbca876SKumar Gala 315acbca876SKumar Gala static struct pci_controller pci1_hose = { 316acbca876SKumar Gala #ifndef CONFIG_PCI_PNP 317acbca876SKumar Gala config_table: pci_mpc8568mds_config_table, 318acbca876SKumar Gala #endif 319acbca876SKumar Gala }; 320acbca876SKumar Gala #endif /* CONFIG_PCI */ 321acbca876SKumar Gala 322acbca876SKumar Gala #ifdef CONFIG_PCIE1 323acbca876SKumar Gala static struct pci_controller pcie1_hose; 324acbca876SKumar Gala #endif /* CONFIG_PCIE1 */ 325acbca876SKumar Gala 326acbca876SKumar Gala int first_free_busno = 0; 327acbca876SKumar Gala 328acbca876SKumar Gala /* 329acbca876SKumar Gala * pib_init() -- Initialize the PCA9555 IO expander on the PIB board 330acbca876SKumar Gala */ 331acbca876SKumar Gala void 332acbca876SKumar Gala pib_init(void) 333acbca876SKumar Gala { 334acbca876SKumar Gala u8 val8, orig_i2c_bus; 335acbca876SKumar Gala /* 336acbca876SKumar Gala * Assign PIB PMC2/3 to PCI bus 337acbca876SKumar Gala */ 338acbca876SKumar Gala 339acbca876SKumar Gala /*switch temporarily to I2C bus #2 */ 340acbca876SKumar Gala orig_i2c_bus = i2c_get_bus_num(); 341acbca876SKumar Gala i2c_set_bus_num(1); 342acbca876SKumar Gala 343acbca876SKumar Gala val8 = 0x00; 344acbca876SKumar Gala i2c_write(0x23, 0x6, 1, &val8, 1); 345acbca876SKumar Gala i2c_write(0x23, 0x7, 1, &val8, 1); 346acbca876SKumar Gala val8 = 0xff; 347acbca876SKumar Gala i2c_write(0x23, 0x2, 1, &val8, 1); 348acbca876SKumar Gala i2c_write(0x23, 0x3, 1, &val8, 1); 349acbca876SKumar Gala 350acbca876SKumar Gala val8 = 0x00; 351acbca876SKumar Gala i2c_write(0x26, 0x6, 1, &val8, 1); 352acbca876SKumar Gala val8 = 0x34; 353acbca876SKumar Gala i2c_write(0x26, 0x7, 1, &val8, 1); 354acbca876SKumar Gala val8 = 0xf9; 355acbca876SKumar Gala i2c_write(0x26, 0x2, 1, &val8, 1); 356acbca876SKumar Gala val8 = 0xff; 357acbca876SKumar Gala i2c_write(0x26, 0x3, 1, &val8, 1); 358acbca876SKumar Gala 359acbca876SKumar Gala val8 = 0x00; 360acbca876SKumar Gala i2c_write(0x27, 0x6, 1, &val8, 1); 361acbca876SKumar Gala i2c_write(0x27, 0x7, 1, &val8, 1); 362acbca876SKumar Gala val8 = 0xff; 363acbca876SKumar Gala i2c_write(0x27, 0x2, 1, &val8, 1); 364acbca876SKumar Gala val8 = 0xef; 365acbca876SKumar Gala i2c_write(0x27, 0x3, 1, &val8, 1); 366acbca876SKumar Gala 367acbca876SKumar Gala asm("eieio"); 368acbca876SKumar Gala } 369acbca876SKumar Gala 370acbca876SKumar Gala #ifdef CONFIG_PCI 371acbca876SKumar Gala void 372acbca876SKumar Gala pci_init_board(void) 373acbca876SKumar Gala { 374acbca876SKumar Gala volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 375acbca876SKumar Gala uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 376acbca876SKumar Gala uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 377acbca876SKumar Gala 378acbca876SKumar Gala #ifdef CONFIG_PCI1 379acbca876SKumar Gala { 380acbca876SKumar Gala pib_init(); 381acbca876SKumar Gala 382acbca876SKumar Gala volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 383acbca876SKumar Gala extern void fsl_pci_init(struct pci_controller *hose); 384acbca876SKumar Gala struct pci_controller *hose = &pci1_hose; 385acbca876SKumar Gala 386acbca876SKumar Gala uint pci_32 = 1; /* PORDEVSR[15] */ 387acbca876SKumar Gala uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 388acbca876SKumar Gala uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 389acbca876SKumar Gala 390acbca876SKumar Gala uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); 391acbca876SKumar Gala 392acbca876SKumar Gala uint pci_speed = 66666000; 393acbca876SKumar Gala 394acbca876SKumar Gala if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 395acbca876SKumar Gala printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", 396acbca876SKumar Gala (pci_32) ? 32 : 64, 397acbca876SKumar Gala (pci_speed == 33333000) ? "33" : 398acbca876SKumar Gala (pci_speed == 66666000) ? "66" : "unknown", 399acbca876SKumar Gala pci_clk_sel ? "sync" : "async", 400acbca876SKumar Gala pci_agent ? "agent" : "host", 401acbca876SKumar Gala pci_arb ? "arbiter" : "external-arbiter" 402acbca876SKumar Gala ); 403acbca876SKumar Gala 404acbca876SKumar Gala /* inbound */ 405acbca876SKumar Gala pci_set_region(hose->regions + 0, 406acbca876SKumar Gala CFG_PCI_MEMORY_BUS, 407acbca876SKumar Gala CFG_PCI_MEMORY_PHYS, 408acbca876SKumar Gala CFG_PCI_MEMORY_SIZE, 409acbca876SKumar Gala PCI_REGION_MEM | PCI_REGION_MEMORY); 410acbca876SKumar Gala 411acbca876SKumar Gala /* outbound memory */ 412acbca876SKumar Gala pci_set_region(hose->regions + 1, 413acbca876SKumar Gala CFG_PCI1_MEM_BASE, 414acbca876SKumar Gala CFG_PCI1_MEM_PHYS, 415acbca876SKumar Gala CFG_PCI1_MEM_SIZE, 416acbca876SKumar Gala PCI_REGION_MEM); 417acbca876SKumar Gala 418acbca876SKumar Gala /* outbound io */ 419acbca876SKumar Gala pci_set_region(hose->regions + 2, 420acbca876SKumar Gala CFG_PCI1_IO_BASE, 421acbca876SKumar Gala CFG_PCI1_IO_PHYS, 422acbca876SKumar Gala CFG_PCI1_IO_SIZE, 423acbca876SKumar Gala PCI_REGION_IO); 424acbca876SKumar Gala 425acbca876SKumar Gala hose->region_count = 3; 426acbca876SKumar Gala 427acbca876SKumar Gala hose->first_busno = first_free_busno; 428acbca876SKumar Gala pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 429acbca876SKumar Gala 430acbca876SKumar Gala fsl_pci_init(hose); 431acbca876SKumar Gala first_free_busno = hose->last_busno+1; 432acbca876SKumar Gala printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 433acbca876SKumar Gala } else { 434acbca876SKumar Gala printf (" PCI: disabled\n"); 435acbca876SKumar Gala } 436acbca876SKumar Gala } 437acbca876SKumar Gala #else 438acbca876SKumar Gala gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 439acbca876SKumar Gala #endif 440acbca876SKumar Gala 441acbca876SKumar Gala #ifdef CONFIG_PCIE1 442acbca876SKumar Gala { 443acbca876SKumar Gala volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 444acbca876SKumar Gala extern void fsl_pci_init(struct pci_controller *hose); 445acbca876SKumar Gala struct pci_controller *hose = &pcie1_hose; 446acbca876SKumar Gala int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 447acbca876SKumar Gala 448acbca876SKumar Gala int pcie_configured = io_sel >= 1; 449acbca876SKumar Gala 450acbca876SKumar Gala if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 451acbca876SKumar Gala printf ("\n PCIE connected to slot as %s (base address %x)", 452acbca876SKumar Gala pcie_ep ? "End Point" : "Root Complex", 453acbca876SKumar Gala (uint)pci); 454acbca876SKumar Gala 455acbca876SKumar Gala if (pci->pme_msg_det) { 456acbca876SKumar Gala pci->pme_msg_det = 0xffffffff; 457acbca876SKumar Gala debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 458acbca876SKumar Gala } 459acbca876SKumar Gala printf ("\n"); 460acbca876SKumar Gala 461acbca876SKumar Gala /* inbound */ 462acbca876SKumar Gala pci_set_region(hose->regions + 0, 463acbca876SKumar Gala CFG_PCI_MEMORY_BUS, 464acbca876SKumar Gala CFG_PCI_MEMORY_PHYS, 465acbca876SKumar Gala CFG_PCI_MEMORY_SIZE, 466acbca876SKumar Gala PCI_REGION_MEM | PCI_REGION_MEMORY); 467acbca876SKumar Gala 468acbca876SKumar Gala /* outbound memory */ 469acbca876SKumar Gala pci_set_region(hose->regions + 1, 470acbca876SKumar Gala CFG_PCIE1_MEM_BASE, 471acbca876SKumar Gala CFG_PCIE1_MEM_PHYS, 472acbca876SKumar Gala CFG_PCIE1_MEM_SIZE, 473acbca876SKumar Gala PCI_REGION_MEM); 474acbca876SKumar Gala 475acbca876SKumar Gala /* outbound io */ 476acbca876SKumar Gala pci_set_region(hose->regions + 2, 477acbca876SKumar Gala CFG_PCIE1_IO_BASE, 478acbca876SKumar Gala CFG_PCIE1_IO_PHYS, 479acbca876SKumar Gala CFG_PCIE1_IO_SIZE, 480acbca876SKumar Gala PCI_REGION_IO); 481acbca876SKumar Gala 482acbca876SKumar Gala hose->region_count = 3; 483acbca876SKumar Gala 484acbca876SKumar Gala hose->first_busno=first_free_busno; 485acbca876SKumar Gala pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 486acbca876SKumar Gala 487acbca876SKumar Gala fsl_pci_init(hose); 488acbca876SKumar Gala printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 489acbca876SKumar Gala 490acbca876SKumar Gala first_free_busno=hose->last_busno+1; 491acbca876SKumar Gala 492acbca876SKumar Gala } else { 493acbca876SKumar Gala printf (" PCIE: disabled\n"); 494acbca876SKumar Gala } 495acbca876SKumar Gala } 496acbca876SKumar Gala #else 497acbca876SKumar Gala gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 498acbca876SKumar Gala #endif 499acbca876SKumar Gala } 500acbca876SKumar Gala #endif /* CONFIG_PCI */ 501acbca876SKumar Gala 502acbca876SKumar Gala #if defined(CONFIG_OF_BOARD_SETUP) 503acbca876SKumar Gala void 504acbca876SKumar Gala ft_board_setup(void *blob, bd_t *bd) 505acbca876SKumar Gala { 506acbca876SKumar Gala int node, tmp[2]; 507acbca876SKumar Gala const char *path; 508acbca876SKumar Gala 509acbca876SKumar Gala ft_cpu_setup(blob, bd); 510acbca876SKumar Gala 511acbca876SKumar Gala node = fdt_path_offset(blob, "/aliases"); 512acbca876SKumar Gala tmp[0] = 0; 513acbca876SKumar Gala if (node >= 0) { 514acbca876SKumar Gala #ifdef CONFIG_PCI1 515acbca876SKumar Gala path = fdt_getprop(blob, node, "pci0", NULL); 516acbca876SKumar Gala if (path) { 517acbca876SKumar Gala tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 518acbca876SKumar Gala do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 519acbca876SKumar Gala } 520acbca876SKumar Gala #endif 521acbca876SKumar Gala #ifdef CONFIG_PCIE1 522acbca876SKumar Gala path = fdt_getprop(blob, node, "pci1", NULL); 523acbca876SKumar Gala if (path) { 524acbca876SKumar Gala tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 525acbca876SKumar Gala do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 526acbca876SKumar Gala } 527acbca876SKumar Gala #endif 528acbca876SKumar Gala } 529acbca876SKumar Gala } 530acbca876SKumar Gala #endif 531