1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2acbca876SKumar Gala /* 3b092072eSZhao Chenhui * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. 4acbca876SKumar Gala * 5acbca876SKumar Gala * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 6acbca876SKumar Gala */ 7acbca876SKumar Gala 8acbca876SKumar Gala #include <common.h> 9acbca876SKumar Gala #include <pci.h> 10acbca876SKumar Gala #include <asm/processor.h> 11e6f5b35bSJon Loeliger #include <asm/mmu.h> 12acbca876SKumar Gala #include <asm/immap_85xx.h> 13c8514622SKumar Gala #include <asm/fsl_pci.h> 145614e71bSYork Sun #include <fsl_ddr_sdram.h> 155d27e02cSKumar Gala #include <asm/fsl_serdes.h> 16a30a549aSJon Loeliger #include <spd_sdram.h> 17acbca876SKumar Gala #include <i2c.h> 18acbca876SKumar Gala #include <ioports.h> 19b08c8c48SMasahiro Yamada #include <linux/libfdt.h> 20acbca876SKumar Gala #include <fdt_support.h> 21acbca876SKumar Gala 22acbca876SKumar Gala #include "bcsr.h" 23acbca876SKumar Gala 24acbca876SKumar Gala const qe_iop_conf_t qe_iop_conf_tab[] = { 25acbca876SKumar Gala /* GETH1 */ 26acbca876SKumar Gala {4, 10, 1, 0, 2}, /* TxD0 */ 27acbca876SKumar Gala {4, 9, 1, 0, 2}, /* TxD1 */ 28acbca876SKumar Gala {4, 8, 1, 0, 2}, /* TxD2 */ 29acbca876SKumar Gala {4, 7, 1, 0, 2}, /* TxD3 */ 30acbca876SKumar Gala {4, 23, 1, 0, 2}, /* TxD4 */ 31acbca876SKumar Gala {4, 22, 1, 0, 2}, /* TxD5 */ 32acbca876SKumar Gala {4, 21, 1, 0, 2}, /* TxD6 */ 33acbca876SKumar Gala {4, 20, 1, 0, 2}, /* TxD7 */ 34acbca876SKumar Gala {4, 15, 2, 0, 2}, /* RxD0 */ 35acbca876SKumar Gala {4, 14, 2, 0, 2}, /* RxD1 */ 36acbca876SKumar Gala {4, 13, 2, 0, 2}, /* RxD2 */ 37acbca876SKumar Gala {4, 12, 2, 0, 2}, /* RxD3 */ 38acbca876SKumar Gala {4, 29, 2, 0, 2}, /* RxD4 */ 39acbca876SKumar Gala {4, 28, 2, 0, 2}, /* RxD5 */ 40acbca876SKumar Gala {4, 27, 2, 0, 2}, /* RxD6 */ 41acbca876SKumar Gala {4, 26, 2, 0, 2}, /* RxD7 */ 42acbca876SKumar Gala {4, 11, 1, 0, 2}, /* TX_EN */ 43acbca876SKumar Gala {4, 24, 1, 0, 2}, /* TX_ER */ 44acbca876SKumar Gala {4, 16, 2, 0, 2}, /* RX_DV */ 45acbca876SKumar Gala {4, 30, 2, 0, 2}, /* RX_ER */ 46acbca876SKumar Gala {4, 17, 2, 0, 2}, /* RX_CLK */ 47acbca876SKumar Gala {4, 19, 1, 0, 2}, /* GTX_CLK */ 48acbca876SKumar Gala {1, 31, 2, 0, 3}, /* GTX125 */ 49acbca876SKumar Gala 50acbca876SKumar Gala /* GETH2 */ 51acbca876SKumar Gala {5, 10, 1, 0, 2}, /* TxD0 */ 52acbca876SKumar Gala {5, 9, 1, 0, 2}, /* TxD1 */ 53acbca876SKumar Gala {5, 8, 1, 0, 2}, /* TxD2 */ 54acbca876SKumar Gala {5, 7, 1, 0, 2}, /* TxD3 */ 55acbca876SKumar Gala {5, 23, 1, 0, 2}, /* TxD4 */ 56acbca876SKumar Gala {5, 22, 1, 0, 2}, /* TxD5 */ 57acbca876SKumar Gala {5, 21, 1, 0, 2}, /* TxD6 */ 58acbca876SKumar Gala {5, 20, 1, 0, 2}, /* TxD7 */ 59acbca876SKumar Gala {5, 15, 2, 0, 2}, /* RxD0 */ 60acbca876SKumar Gala {5, 14, 2, 0, 2}, /* RxD1 */ 61acbca876SKumar Gala {5, 13, 2, 0, 2}, /* RxD2 */ 62acbca876SKumar Gala {5, 12, 2, 0, 2}, /* RxD3 */ 63acbca876SKumar Gala {5, 29, 2, 0, 2}, /* RxD4 */ 64acbca876SKumar Gala {5, 28, 2, 0, 2}, /* RxD5 */ 65acbca876SKumar Gala {5, 27, 2, 0, 3}, /* RxD6 */ 66acbca876SKumar Gala {5, 26, 2, 0, 2}, /* RxD7 */ 67acbca876SKumar Gala {5, 11, 1, 0, 2}, /* TX_EN */ 68acbca876SKumar Gala {5, 24, 1, 0, 2}, /* TX_ER */ 69acbca876SKumar Gala {5, 16, 2, 0, 2}, /* RX_DV */ 70acbca876SKumar Gala {5, 30, 2, 0, 2}, /* RX_ER */ 71acbca876SKumar Gala {5, 17, 2, 0, 2}, /* RX_CLK */ 72acbca876SKumar Gala {5, 19, 1, 0, 2}, /* GTX_CLK */ 73acbca876SKumar Gala {1, 31, 2, 0, 3}, /* GTX125 */ 74acbca876SKumar Gala {4, 6, 3, 0, 2}, /* MDIO */ 75acbca876SKumar Gala {4, 5, 1, 0, 2}, /* MDC */ 7664d4bcb0SAnton Vorontsov 7764d4bcb0SAnton Vorontsov /* UART1 */ 7864d4bcb0SAnton Vorontsov {2, 0, 1, 0, 2}, /* UART_SOUT1 */ 7964d4bcb0SAnton Vorontsov {2, 1, 1, 0, 2}, /* UART_RTS1 */ 8064d4bcb0SAnton Vorontsov {2, 2, 2, 0, 2}, /* UART_CTS1 */ 8164d4bcb0SAnton Vorontsov {2, 3, 2, 0, 2}, /* UART_SIN1 */ 8264d4bcb0SAnton Vorontsov 83acbca876SKumar Gala {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 84acbca876SKumar Gala }; 85acbca876SKumar Gala 86acbca876SKumar Gala void local_bus_init(void); 87acbca876SKumar Gala 88acbca876SKumar Gala int board_early_init_f (void) 89acbca876SKumar Gala { 90acbca876SKumar Gala /* 91acbca876SKumar Gala * Initialize local bus. 92acbca876SKumar Gala */ 93acbca876SKumar Gala local_bus_init (); 94acbca876SKumar Gala 95acbca876SKumar Gala enable_8568mds_duart(); 96acbca876SKumar Gala enable_8568mds_flash_write(); 97ad162249SAnton Vorontsov #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 98ad162249SAnton Vorontsov reset_8568mds_uccs(); 99ad162249SAnton Vorontsov #endif 100acbca876SKumar Gala #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) 101acbca876SKumar Gala enable_8568mds_qe_mdio(); 102acbca876SKumar Gala #endif 103acbca876SKumar Gala 1046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_I2C2_OFFSET 105acbca876SKumar Gala /* Enable I2C2_SCL and I2C2_SDA */ 106acbca876SKumar Gala volatile struct par_io *port_c; 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140); 108acbca876SKumar Gala port_c->cpdir2 |= 0x0f000000; 109acbca876SKumar Gala port_c->cppar2 &= ~0x0f000000; 110acbca876SKumar Gala port_c->cppar2 |= 0x0a000000; 111acbca876SKumar Gala #endif 112acbca876SKumar Gala 113acbca876SKumar Gala return 0; 114acbca876SKumar Gala } 115acbca876SKumar Gala 116acbca876SKumar Gala int checkboard (void) 117acbca876SKumar Gala { 118acbca876SKumar Gala printf ("Board: 8568 MDS\n"); 119acbca876SKumar Gala 120acbca876SKumar Gala return 0; 121acbca876SKumar Gala } 122acbca876SKumar Gala 123acbca876SKumar Gala /* 124acbca876SKumar Gala * Initialize Local Bus 125acbca876SKumar Gala */ 126acbca876SKumar Gala void 127acbca876SKumar Gala local_bus_init(void) 128acbca876SKumar Gala { 1296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 130f51cdaf1SBecky Bruce volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 131acbca876SKumar Gala 132acbca876SKumar Gala uint clkdiv; 133acbca876SKumar Gala sys_info_t sysinfo; 134acbca876SKumar Gala 135acbca876SKumar Gala get_sys_info(&sysinfo); 136a5d212a2STrent Piepho clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 137acbca876SKumar Gala 138acbca876SKumar Gala gur->lbiuiplldcr1 = 0x00078080; 139acbca876SKumar Gala if (clkdiv == 16) { 140acbca876SKumar Gala gur->lbiuiplldcr0 = 0x7c0f1bf0; 141acbca876SKumar Gala } else if (clkdiv == 8) { 142acbca876SKumar Gala gur->lbiuiplldcr0 = 0x6c0f1bf0; 143acbca876SKumar Gala } else if (clkdiv == 4) { 144acbca876SKumar Gala gur->lbiuiplldcr0 = 0x5c0f1bf0; 145acbca876SKumar Gala } 146acbca876SKumar Gala 147acbca876SKumar Gala lbc->lcrr |= 0x00030000; 148acbca876SKumar Gala 149acbca876SKumar Gala asm("sync;isync;msync"); 150acbca876SKumar Gala } 151acbca876SKumar Gala 152acbca876SKumar Gala /* 153acbca876SKumar Gala * Initialize SDRAM memory on the Local Bus. 154acbca876SKumar Gala */ 15570961ba4SBecky Bruce void lbc_sdram_init(void) 156acbca876SKumar Gala { 1576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 158acbca876SKumar Gala 159acbca876SKumar Gala uint idx; 160f51cdaf1SBecky Bruce volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 1616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 162acbca876SKumar Gala uint lsdmr_common; 163acbca876SKumar Gala 1647ea3871eSBecky Bruce puts("LBC SDRAM: "); 1657ea3871eSBecky Bruce print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, 1667ea3871eSBecky Bruce "\n "); 167acbca876SKumar Gala 168acbca876SKumar Gala /* 169acbca876SKumar Gala * Setup SDRAM Base and Option Registers 170acbca876SKumar Gala */ 171f51cdaf1SBecky Bruce set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 172f51cdaf1SBecky Bruce set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 173acbca876SKumar Gala asm("msync"); 174acbca876SKumar Gala 1756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lbcr = CONFIG_SYS_LBC_LBCR; 176acbca876SKumar Gala asm("msync"); 177acbca876SKumar Gala 1786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lsrt = CONFIG_SYS_LBC_LSRT; 1796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 180acbca876SKumar Gala asm("msync"); 181acbca876SKumar Gala 182acbca876SKumar Gala /* 183acbca876SKumar Gala * MPC8568 uses "new" 15-16 style addressing. 184acbca876SKumar Gala */ 1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 186b0fe93edSKumar Gala lsdmr_common |= LSDMR_BSMA1516; 187acbca876SKumar Gala 188acbca876SKumar Gala /* 189acbca876SKumar Gala * Issue PRECHARGE ALL command. 190acbca876SKumar Gala */ 191b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 192acbca876SKumar Gala asm("sync;msync"); 193acbca876SKumar Gala *sdram_addr = 0xff; 194acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 195acbca876SKumar Gala udelay(100); 196acbca876SKumar Gala 197acbca876SKumar Gala /* 198acbca876SKumar Gala * Issue 8 AUTO REFRESH commands. 199acbca876SKumar Gala */ 200acbca876SKumar Gala for (idx = 0; idx < 8; idx++) { 201b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 202acbca876SKumar Gala asm("sync;msync"); 203acbca876SKumar Gala *sdram_addr = 0xff; 204acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 205acbca876SKumar Gala udelay(100); 206acbca876SKumar Gala } 207acbca876SKumar Gala 208acbca876SKumar Gala /* 209acbca876SKumar Gala * Issue 8 MODE-set command. 210acbca876SKumar Gala */ 211b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 212acbca876SKumar Gala asm("sync;msync"); 213acbca876SKumar Gala *sdram_addr = 0xff; 214acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 215acbca876SKumar Gala udelay(100); 216acbca876SKumar Gala 217acbca876SKumar Gala /* 218acbca876SKumar Gala * Issue NORMAL OP command. 219acbca876SKumar Gala */ 220b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 221acbca876SKumar Gala asm("sync;msync"); 222acbca876SKumar Gala *sdram_addr = 0xff; 223acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 224acbca876SKumar Gala udelay(200); /* Overkill. Must wait > 200 bus cycles */ 225acbca876SKumar Gala 226acbca876SKumar Gala #endif /* enable SDRAM init */ 227acbca876SKumar Gala } 228acbca876SKumar Gala 229acbca876SKumar Gala #if defined(CONFIG_PCI) 230acbca876SKumar Gala #ifndef CONFIG_PCI_PNP 231acbca876SKumar Gala static struct pci_config_table pci_mpc8568mds_config_table[] = { 232acbca876SKumar Gala { 233acbca876SKumar Gala PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 234acbca876SKumar Gala pci_cfgfunc_config_device, 235acbca876SKumar Gala {PCI_ENET0_IOADDR, 236acbca876SKumar Gala PCI_ENET0_MEMADDR, 237acbca876SKumar Gala PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} 238acbca876SKumar Gala }, 239acbca876SKumar Gala {} 240acbca876SKumar Gala }; 241acbca876SKumar Gala #endif 242acbca876SKumar Gala 243b092072eSZhao Chenhui static struct pci_controller pci1_hose; 244acbca876SKumar Gala #endif /* CONFIG_PCI */ 245acbca876SKumar Gala 246acbca876SKumar Gala /* 247acbca876SKumar Gala * pib_init() -- Initialize the PCA9555 IO expander on the PIB board 248acbca876SKumar Gala */ 249acbca876SKumar Gala void 250acbca876SKumar Gala pib_init(void) 251acbca876SKumar Gala { 252acbca876SKumar Gala u8 val8, orig_i2c_bus; 253acbca876SKumar Gala /* 254acbca876SKumar Gala * Assign PIB PMC2/3 to PCI bus 255acbca876SKumar Gala */ 256acbca876SKumar Gala 257acbca876SKumar Gala /*switch temporarily to I2C bus #2 */ 258acbca876SKumar Gala orig_i2c_bus = i2c_get_bus_num(); 259acbca876SKumar Gala i2c_set_bus_num(1); 260acbca876SKumar Gala 261acbca876SKumar Gala val8 = 0x00; 262acbca876SKumar Gala i2c_write(0x23, 0x6, 1, &val8, 1); 263acbca876SKumar Gala i2c_write(0x23, 0x7, 1, &val8, 1); 264acbca876SKumar Gala val8 = 0xff; 265acbca876SKumar Gala i2c_write(0x23, 0x2, 1, &val8, 1); 266acbca876SKumar Gala i2c_write(0x23, 0x3, 1, &val8, 1); 267acbca876SKumar Gala 268acbca876SKumar Gala val8 = 0x00; 269acbca876SKumar Gala i2c_write(0x26, 0x6, 1, &val8, 1); 270acbca876SKumar Gala val8 = 0x34; 271acbca876SKumar Gala i2c_write(0x26, 0x7, 1, &val8, 1); 272acbca876SKumar Gala val8 = 0xf9; 273acbca876SKumar Gala i2c_write(0x26, 0x2, 1, &val8, 1); 274acbca876SKumar Gala val8 = 0xff; 275acbca876SKumar Gala i2c_write(0x26, 0x3, 1, &val8, 1); 276acbca876SKumar Gala 277acbca876SKumar Gala val8 = 0x00; 278acbca876SKumar Gala i2c_write(0x27, 0x6, 1, &val8, 1); 279acbca876SKumar Gala i2c_write(0x27, 0x7, 1, &val8, 1); 280acbca876SKumar Gala val8 = 0xff; 281acbca876SKumar Gala i2c_write(0x27, 0x2, 1, &val8, 1); 282acbca876SKumar Gala val8 = 0xef; 283acbca876SKumar Gala i2c_write(0x27, 0x3, 1, &val8, 1); 284acbca876SKumar Gala 285acbca876SKumar Gala asm("eieio"); 286502dd36bSKumar Gala i2c_set_bus_num(orig_i2c_bus); 287acbca876SKumar Gala } 288acbca876SKumar Gala 289acbca876SKumar Gala #ifdef CONFIG_PCI 2904681457eSKumar Gala void pci_init_board(void) 291acbca876SKumar Gala { 2926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 2933f6f9d76SKumar Gala int first_free_busno = 0; 2943f6f9d76SKumar Gala #ifdef CONFIG_PCI1 2953f6f9d76SKumar Gala struct fsl_pci_info pci_info; 2964681457eSKumar Gala u32 devdisr, pordevsr, io_sel; 2974681457eSKumar Gala u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 2984681457eSKumar Gala 2994681457eSKumar Gala devdisr = in_be32(&gur->devdisr); 3004681457eSKumar Gala pordevsr = in_be32(&gur->pordevsr); 3014681457eSKumar Gala porpllsr = in_be32(&gur->porpllsr); 3024681457eSKumar Gala io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 3034681457eSKumar Gala 3044681457eSKumar Gala debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 305acbca876SKumar Gala 3064681457eSKumar Gala pci_speed = 66666000; 3074681457eSKumar Gala pci_32 = 1; 3084681457eSKumar Gala pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 3094681457eSKumar Gala pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 310acbca876SKumar Gala 3114681457eSKumar Gala if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 3123f6f9d76SKumar Gala SET_STD_PCI_INFO(pci_info, 1); 3133f6f9d76SKumar Gala set_next_law(pci_info.mem_phys, 3143f6f9d76SKumar Gala law_size_bits(pci_info.mem_size), pci_info.law); 3153f6f9d76SKumar Gala set_next_law(pci_info.io_phys, 3163f6f9d76SKumar Gala law_size_bits(pci_info.io_size), pci_info.law); 3173f6f9d76SKumar Gala 3183f6f9d76SKumar Gala pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 3198ca78f2cSPeter Tyser printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 320acbca876SKumar Gala (pci_32) ? 32 : 64, 321acbca876SKumar Gala (pci_speed == 33333000) ? "33" : 322acbca876SKumar Gala (pci_speed == 66666000) ? "66" : "unknown", 323acbca876SKumar Gala pci_clk_sel ? "sync" : "async", 324acbca876SKumar Gala pci_agent ? "agent" : "host", 3254681457eSKumar Gala pci_arb ? "arbiter" : "external-arbiter", 3263f6f9d76SKumar Gala pci_info.regs); 327acbca876SKumar Gala 328b092072eSZhao Chenhui #ifndef CONFIG_PCI_PNP 329b092072eSZhao Chenhui pci1_hose.config_table = pci_mpc8568mds_config_table; 330b092072eSZhao Chenhui #endif 3313f6f9d76SKumar Gala first_free_busno = fsl_pci_init_port(&pci_info, 3324681457eSKumar Gala &pci1_hose, first_free_busno); 333acbca876SKumar Gala } else { 334acbca876SKumar Gala printf("PCI: disabled\n"); 335acbca876SKumar Gala } 3364681457eSKumar Gala 3374681457eSKumar Gala puts("\n"); 338acbca876SKumar Gala #else 3394681457eSKumar Gala setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 340acbca876SKumar Gala #endif 341acbca876SKumar Gala 3423f6f9d76SKumar Gala fsl_pcie_init_board(first_free_busno); 343acbca876SKumar Gala } 344acbca876SKumar Gala #endif /* CONFIG_PCI */ 345acbca876SKumar Gala 346acbca876SKumar Gala #if defined(CONFIG_OF_BOARD_SETUP) 347e895a4b0SSimon Glass int ft_board_setup(void *blob, bd_t *bd) 3482dba0deaSKumar Gala { 349acbca876SKumar Gala ft_cpu_setup(blob, bd); 350acbca876SKumar Gala 3516525d51fSKumar Gala FT_FSL_PCI_SETUP; 352e895a4b0SSimon Glass 353e895a4b0SSimon Glass return 0; 354acbca876SKumar Gala } 355acbca876SKumar Gala #endif 356