1acbca876SKumar Gala /* 2*6525d51fSKumar Gala * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. 3acbca876SKumar Gala * 4acbca876SKumar Gala * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5acbca876SKumar Gala * 6acbca876SKumar Gala * See file CREDITS for list of people who contributed to this 7acbca876SKumar Gala * project. 8acbca876SKumar Gala * 9acbca876SKumar Gala * This program is free software; you can redistribute it and/or 10acbca876SKumar Gala * modify it under the terms of the GNU General Public License as 11acbca876SKumar Gala * published by the Free Software Foundation; either version 2 of 12acbca876SKumar Gala * the License, or (at your option) any later version. 13acbca876SKumar Gala * 14acbca876SKumar Gala * This program is distributed in the hope that it will be useful, 15acbca876SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 16acbca876SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17acbca876SKumar Gala * GNU General Public License for more details. 18acbca876SKumar Gala * 19acbca876SKumar Gala * You should have received a copy of the GNU General Public License 20acbca876SKumar Gala * along with this program; if not, write to the Free Software 21acbca876SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22acbca876SKumar Gala * MA 02111-1307 USA 23acbca876SKumar Gala */ 24acbca876SKumar Gala 25acbca876SKumar Gala #include <common.h> 26acbca876SKumar Gala #include <pci.h> 27acbca876SKumar Gala #include <asm/processor.h> 28e6f5b35bSJon Loeliger #include <asm/mmu.h> 29acbca876SKumar Gala #include <asm/immap_85xx.h> 30c8514622SKumar Gala #include <asm/fsl_pci.h> 31e6f5b35bSJon Loeliger #include <asm/fsl_ddr_sdram.h> 32a30a549aSJon Loeliger #include <spd_sdram.h> 33acbca876SKumar Gala #include <i2c.h> 34acbca876SKumar Gala #include <ioports.h> 35acbca876SKumar Gala #include <libfdt.h> 36acbca876SKumar Gala #include <fdt_support.h> 37acbca876SKumar Gala 38acbca876SKumar Gala #include "bcsr.h" 39acbca876SKumar Gala 40acbca876SKumar Gala const qe_iop_conf_t qe_iop_conf_tab[] = { 41acbca876SKumar Gala /* GETH1 */ 42acbca876SKumar Gala {4, 10, 1, 0, 2}, /* TxD0 */ 43acbca876SKumar Gala {4, 9, 1, 0, 2}, /* TxD1 */ 44acbca876SKumar Gala {4, 8, 1, 0, 2}, /* TxD2 */ 45acbca876SKumar Gala {4, 7, 1, 0, 2}, /* TxD3 */ 46acbca876SKumar Gala {4, 23, 1, 0, 2}, /* TxD4 */ 47acbca876SKumar Gala {4, 22, 1, 0, 2}, /* TxD5 */ 48acbca876SKumar Gala {4, 21, 1, 0, 2}, /* TxD6 */ 49acbca876SKumar Gala {4, 20, 1, 0, 2}, /* TxD7 */ 50acbca876SKumar Gala {4, 15, 2, 0, 2}, /* RxD0 */ 51acbca876SKumar Gala {4, 14, 2, 0, 2}, /* RxD1 */ 52acbca876SKumar Gala {4, 13, 2, 0, 2}, /* RxD2 */ 53acbca876SKumar Gala {4, 12, 2, 0, 2}, /* RxD3 */ 54acbca876SKumar Gala {4, 29, 2, 0, 2}, /* RxD4 */ 55acbca876SKumar Gala {4, 28, 2, 0, 2}, /* RxD5 */ 56acbca876SKumar Gala {4, 27, 2, 0, 2}, /* RxD6 */ 57acbca876SKumar Gala {4, 26, 2, 0, 2}, /* RxD7 */ 58acbca876SKumar Gala {4, 11, 1, 0, 2}, /* TX_EN */ 59acbca876SKumar Gala {4, 24, 1, 0, 2}, /* TX_ER */ 60acbca876SKumar Gala {4, 16, 2, 0, 2}, /* RX_DV */ 61acbca876SKumar Gala {4, 30, 2, 0, 2}, /* RX_ER */ 62acbca876SKumar Gala {4, 17, 2, 0, 2}, /* RX_CLK */ 63acbca876SKumar Gala {4, 19, 1, 0, 2}, /* GTX_CLK */ 64acbca876SKumar Gala {1, 31, 2, 0, 3}, /* GTX125 */ 65acbca876SKumar Gala 66acbca876SKumar Gala /* GETH2 */ 67acbca876SKumar Gala {5, 10, 1, 0, 2}, /* TxD0 */ 68acbca876SKumar Gala {5, 9, 1, 0, 2}, /* TxD1 */ 69acbca876SKumar Gala {5, 8, 1, 0, 2}, /* TxD2 */ 70acbca876SKumar Gala {5, 7, 1, 0, 2}, /* TxD3 */ 71acbca876SKumar Gala {5, 23, 1, 0, 2}, /* TxD4 */ 72acbca876SKumar Gala {5, 22, 1, 0, 2}, /* TxD5 */ 73acbca876SKumar Gala {5, 21, 1, 0, 2}, /* TxD6 */ 74acbca876SKumar Gala {5, 20, 1, 0, 2}, /* TxD7 */ 75acbca876SKumar Gala {5, 15, 2, 0, 2}, /* RxD0 */ 76acbca876SKumar Gala {5, 14, 2, 0, 2}, /* RxD1 */ 77acbca876SKumar Gala {5, 13, 2, 0, 2}, /* RxD2 */ 78acbca876SKumar Gala {5, 12, 2, 0, 2}, /* RxD3 */ 79acbca876SKumar Gala {5, 29, 2, 0, 2}, /* RxD4 */ 80acbca876SKumar Gala {5, 28, 2, 0, 2}, /* RxD5 */ 81acbca876SKumar Gala {5, 27, 2, 0, 3}, /* RxD6 */ 82acbca876SKumar Gala {5, 26, 2, 0, 2}, /* RxD7 */ 83acbca876SKumar Gala {5, 11, 1, 0, 2}, /* TX_EN */ 84acbca876SKumar Gala {5, 24, 1, 0, 2}, /* TX_ER */ 85acbca876SKumar Gala {5, 16, 2, 0, 2}, /* RX_DV */ 86acbca876SKumar Gala {5, 30, 2, 0, 2}, /* RX_ER */ 87acbca876SKumar Gala {5, 17, 2, 0, 2}, /* RX_CLK */ 88acbca876SKumar Gala {5, 19, 1, 0, 2}, /* GTX_CLK */ 89acbca876SKumar Gala {1, 31, 2, 0, 3}, /* GTX125 */ 90acbca876SKumar Gala {4, 6, 3, 0, 2}, /* MDIO */ 91acbca876SKumar Gala {4, 5, 1, 0, 2}, /* MDC */ 9264d4bcb0SAnton Vorontsov 9364d4bcb0SAnton Vorontsov /* UART1 */ 9464d4bcb0SAnton Vorontsov {2, 0, 1, 0, 2}, /* UART_SOUT1 */ 9564d4bcb0SAnton Vorontsov {2, 1, 1, 0, 2}, /* UART_RTS1 */ 9664d4bcb0SAnton Vorontsov {2, 2, 2, 0, 2}, /* UART_CTS1 */ 9764d4bcb0SAnton Vorontsov {2, 3, 2, 0, 2}, /* UART_SIN1 */ 9864d4bcb0SAnton Vorontsov 99acbca876SKumar Gala {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 100acbca876SKumar Gala }; 101acbca876SKumar Gala 102acbca876SKumar Gala void local_bus_init(void); 103acbca876SKumar Gala void sdram_init(void); 104acbca876SKumar Gala 105acbca876SKumar Gala int board_early_init_f (void) 106acbca876SKumar Gala { 107acbca876SKumar Gala /* 108acbca876SKumar Gala * Initialize local bus. 109acbca876SKumar Gala */ 110acbca876SKumar Gala local_bus_init (); 111acbca876SKumar Gala 112acbca876SKumar Gala enable_8568mds_duart(); 113acbca876SKumar Gala enable_8568mds_flash_write(); 114ad162249SAnton Vorontsov #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 115ad162249SAnton Vorontsov reset_8568mds_uccs(); 116ad162249SAnton Vorontsov #endif 117acbca876SKumar Gala #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) 118acbca876SKumar Gala enable_8568mds_qe_mdio(); 119acbca876SKumar Gala #endif 120acbca876SKumar Gala 1216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_I2C2_OFFSET 122acbca876SKumar Gala /* Enable I2C2_SCL and I2C2_SDA */ 123acbca876SKumar Gala volatile struct par_io *port_c; 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140); 125acbca876SKumar Gala port_c->cpdir2 |= 0x0f000000; 126acbca876SKumar Gala port_c->cppar2 &= ~0x0f000000; 127acbca876SKumar Gala port_c->cppar2 |= 0x0a000000; 128acbca876SKumar Gala #endif 129acbca876SKumar Gala 130acbca876SKumar Gala return 0; 131acbca876SKumar Gala } 132acbca876SKumar Gala 133acbca876SKumar Gala int checkboard (void) 134acbca876SKumar Gala { 135acbca876SKumar Gala printf ("Board: 8568 MDS\n"); 136acbca876SKumar Gala 137acbca876SKumar Gala return 0; 138acbca876SKumar Gala } 139acbca876SKumar Gala 1409973e3c6SBecky Bruce phys_size_t 141acbca876SKumar Gala initdram(int board_type) 142acbca876SKumar Gala { 143acbca876SKumar Gala long dram_size = 0; 144acbca876SKumar Gala 145acbca876SKumar Gala puts("Initializing\n"); 146acbca876SKumar Gala 147acbca876SKumar Gala #if defined(CONFIG_DDR_DLL) 148acbca876SKumar Gala { 149acbca876SKumar Gala /* 150acbca876SKumar Gala * Work around to stabilize DDR DLL MSYNC_IN. 151acbca876SKumar Gala * Errata DDR9 seems to have been fixed. 152acbca876SKumar Gala * This is now the workaround for Errata DDR11: 153acbca876SKumar Gala * Override DLL = 1, Course Adj = 1, Tap Select = 0 154acbca876SKumar Gala */ 155acbca876SKumar Gala 1566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 157acbca876SKumar Gala 158acbca876SKumar Gala gur->ddrdllcr = 0x81000000; 159acbca876SKumar Gala asm("sync;isync;msync"); 160acbca876SKumar Gala udelay(200); 161acbca876SKumar Gala } 162acbca876SKumar Gala #endif 163e6f5b35bSJon Loeliger 164e6f5b35bSJon Loeliger dram_size = fsl_ddr_sdram(); 165e6f5b35bSJon Loeliger dram_size = setup_ddr_tlbs(dram_size / 0x100000); 166e6f5b35bSJon Loeliger dram_size *= 0x100000; 167acbca876SKumar Gala 168acbca876SKumar Gala /* 169acbca876SKumar Gala * SDRAM Initialization 170acbca876SKumar Gala */ 171acbca876SKumar Gala sdram_init(); 172acbca876SKumar Gala 173acbca876SKumar Gala puts(" DDR: "); 174acbca876SKumar Gala return dram_size; 175acbca876SKumar Gala } 176acbca876SKumar Gala 177acbca876SKumar Gala /* 178acbca876SKumar Gala * Initialize Local Bus 179acbca876SKumar Gala */ 180acbca876SKumar Gala void 181acbca876SKumar Gala local_bus_init(void) 182acbca876SKumar Gala { 1836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 184f51cdaf1SBecky Bruce volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 185acbca876SKumar Gala 186acbca876SKumar Gala uint clkdiv; 187acbca876SKumar Gala uint lbc_hz; 188acbca876SKumar Gala sys_info_t sysinfo; 189acbca876SKumar Gala 190acbca876SKumar Gala get_sys_info(&sysinfo); 191a5d212a2STrent Piepho clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 192acbca876SKumar Gala lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 193acbca876SKumar Gala 194acbca876SKumar Gala gur->lbiuiplldcr1 = 0x00078080; 195acbca876SKumar Gala if (clkdiv == 16) { 196acbca876SKumar Gala gur->lbiuiplldcr0 = 0x7c0f1bf0; 197acbca876SKumar Gala } else if (clkdiv == 8) { 198acbca876SKumar Gala gur->lbiuiplldcr0 = 0x6c0f1bf0; 199acbca876SKumar Gala } else if (clkdiv == 4) { 200acbca876SKumar Gala gur->lbiuiplldcr0 = 0x5c0f1bf0; 201acbca876SKumar Gala } 202acbca876SKumar Gala 203acbca876SKumar Gala lbc->lcrr |= 0x00030000; 204acbca876SKumar Gala 205acbca876SKumar Gala asm("sync;isync;msync"); 206acbca876SKumar Gala } 207acbca876SKumar Gala 208acbca876SKumar Gala /* 209acbca876SKumar Gala * Initialize SDRAM memory on the Local Bus. 210acbca876SKumar Gala */ 211acbca876SKumar Gala void 212acbca876SKumar Gala sdram_init(void) 213acbca876SKumar Gala { 2146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 215acbca876SKumar Gala 216acbca876SKumar Gala uint idx; 217f51cdaf1SBecky Bruce volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 2186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 219acbca876SKumar Gala uint lsdmr_common; 220acbca876SKumar Gala 221acbca876SKumar Gala puts(" SDRAM: "); 222acbca876SKumar Gala 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 224acbca876SKumar Gala 225acbca876SKumar Gala /* 226acbca876SKumar Gala * Setup SDRAM Base and Option Registers 227acbca876SKumar Gala */ 228f51cdaf1SBecky Bruce set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 229f51cdaf1SBecky Bruce set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 230acbca876SKumar Gala asm("msync"); 231acbca876SKumar Gala 2326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lbcr = CONFIG_SYS_LBC_LBCR; 233acbca876SKumar Gala asm("msync"); 234acbca876SKumar Gala 2356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lsrt = CONFIG_SYS_LBC_LSRT; 2366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 237acbca876SKumar Gala asm("msync"); 238acbca876SKumar Gala 239acbca876SKumar Gala /* 240acbca876SKumar Gala * MPC8568 uses "new" 15-16 style addressing. 241acbca876SKumar Gala */ 2426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 243b0fe93edSKumar Gala lsdmr_common |= LSDMR_BSMA1516; 244acbca876SKumar Gala 245acbca876SKumar Gala /* 246acbca876SKumar Gala * Issue PRECHARGE ALL command. 247acbca876SKumar Gala */ 248b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 249acbca876SKumar Gala asm("sync;msync"); 250acbca876SKumar Gala *sdram_addr = 0xff; 251acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 252acbca876SKumar Gala udelay(100); 253acbca876SKumar Gala 254acbca876SKumar Gala /* 255acbca876SKumar Gala * Issue 8 AUTO REFRESH commands. 256acbca876SKumar Gala */ 257acbca876SKumar Gala for (idx = 0; idx < 8; idx++) { 258b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 259acbca876SKumar Gala asm("sync;msync"); 260acbca876SKumar Gala *sdram_addr = 0xff; 261acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 262acbca876SKumar Gala udelay(100); 263acbca876SKumar Gala } 264acbca876SKumar Gala 265acbca876SKumar Gala /* 266acbca876SKumar Gala * Issue 8 MODE-set command. 267acbca876SKumar Gala */ 268b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 269acbca876SKumar Gala asm("sync;msync"); 270acbca876SKumar Gala *sdram_addr = 0xff; 271acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 272acbca876SKumar Gala udelay(100); 273acbca876SKumar Gala 274acbca876SKumar Gala /* 275acbca876SKumar Gala * Issue NORMAL OP command. 276acbca876SKumar Gala */ 277b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 278acbca876SKumar Gala asm("sync;msync"); 279acbca876SKumar Gala *sdram_addr = 0xff; 280acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 281acbca876SKumar Gala udelay(200); /* Overkill. Must wait > 200 bus cycles */ 282acbca876SKumar Gala 283acbca876SKumar Gala #endif /* enable SDRAM init */ 284acbca876SKumar Gala } 285acbca876SKumar Gala 286acbca876SKumar Gala #if defined(CONFIG_PCI) 287acbca876SKumar Gala #ifndef CONFIG_PCI_PNP 288acbca876SKumar Gala static struct pci_config_table pci_mpc8568mds_config_table[] = { 289acbca876SKumar Gala { 290acbca876SKumar Gala PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 291acbca876SKumar Gala pci_cfgfunc_config_device, 292acbca876SKumar Gala {PCI_ENET0_IOADDR, 293acbca876SKumar Gala PCI_ENET0_MEMADDR, 294acbca876SKumar Gala PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} 295acbca876SKumar Gala }, 296acbca876SKumar Gala {} 297acbca876SKumar Gala }; 298acbca876SKumar Gala #endif 299acbca876SKumar Gala 300acbca876SKumar Gala static struct pci_controller pci1_hose = { 301acbca876SKumar Gala #ifndef CONFIG_PCI_PNP 302acbca876SKumar Gala config_table: pci_mpc8568mds_config_table, 303acbca876SKumar Gala #endif 304acbca876SKumar Gala }; 305acbca876SKumar Gala #endif /* CONFIG_PCI */ 306acbca876SKumar Gala 307acbca876SKumar Gala #ifdef CONFIG_PCIE1 308acbca876SKumar Gala static struct pci_controller pcie1_hose; 309acbca876SKumar Gala #endif /* CONFIG_PCIE1 */ 310acbca876SKumar Gala 311acbca876SKumar Gala /* 312acbca876SKumar Gala * pib_init() -- Initialize the PCA9555 IO expander on the PIB board 313acbca876SKumar Gala */ 314acbca876SKumar Gala void 315acbca876SKumar Gala pib_init(void) 316acbca876SKumar Gala { 317acbca876SKumar Gala u8 val8, orig_i2c_bus; 318acbca876SKumar Gala /* 319acbca876SKumar Gala * Assign PIB PMC2/3 to PCI bus 320acbca876SKumar Gala */ 321acbca876SKumar Gala 322acbca876SKumar Gala /*switch temporarily to I2C bus #2 */ 323acbca876SKumar Gala orig_i2c_bus = i2c_get_bus_num(); 324acbca876SKumar Gala i2c_set_bus_num(1); 325acbca876SKumar Gala 326acbca876SKumar Gala val8 = 0x00; 327acbca876SKumar Gala i2c_write(0x23, 0x6, 1, &val8, 1); 328acbca876SKumar Gala i2c_write(0x23, 0x7, 1, &val8, 1); 329acbca876SKumar Gala val8 = 0xff; 330acbca876SKumar Gala i2c_write(0x23, 0x2, 1, &val8, 1); 331acbca876SKumar Gala i2c_write(0x23, 0x3, 1, &val8, 1); 332acbca876SKumar Gala 333acbca876SKumar Gala val8 = 0x00; 334acbca876SKumar Gala i2c_write(0x26, 0x6, 1, &val8, 1); 335acbca876SKumar Gala val8 = 0x34; 336acbca876SKumar Gala i2c_write(0x26, 0x7, 1, &val8, 1); 337acbca876SKumar Gala val8 = 0xf9; 338acbca876SKumar Gala i2c_write(0x26, 0x2, 1, &val8, 1); 339acbca876SKumar Gala val8 = 0xff; 340acbca876SKumar Gala i2c_write(0x26, 0x3, 1, &val8, 1); 341acbca876SKumar Gala 342acbca876SKumar Gala val8 = 0x00; 343acbca876SKumar Gala i2c_write(0x27, 0x6, 1, &val8, 1); 344acbca876SKumar Gala i2c_write(0x27, 0x7, 1, &val8, 1); 345acbca876SKumar Gala val8 = 0xff; 346acbca876SKumar Gala i2c_write(0x27, 0x2, 1, &val8, 1); 347acbca876SKumar Gala val8 = 0xef; 348acbca876SKumar Gala i2c_write(0x27, 0x3, 1, &val8, 1); 349acbca876SKumar Gala 350acbca876SKumar Gala asm("eieio"); 351acbca876SKumar Gala } 352acbca876SKumar Gala 353acbca876SKumar Gala #ifdef CONFIG_PCI 3544681457eSKumar Gala void pci_init_board(void) 355acbca876SKumar Gala { 3566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 3574681457eSKumar Gala struct fsl_pci_info pci_info[2]; 3584681457eSKumar Gala u32 devdisr, pordevsr, io_sel; 3594681457eSKumar Gala u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 3604681457eSKumar Gala int first_free_busno = 0; 3614681457eSKumar Gala int num = 0; 3624681457eSKumar Gala 3634681457eSKumar Gala int pcie_ep, pcie_configured; 3644681457eSKumar Gala 3654681457eSKumar Gala devdisr = in_be32(&gur->devdisr); 3664681457eSKumar Gala pordevsr = in_be32(&gur->pordevsr); 3674681457eSKumar Gala porpllsr = in_be32(&gur->porpllsr); 3684681457eSKumar Gala io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 3694681457eSKumar Gala 3704681457eSKumar Gala debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 371acbca876SKumar Gala 372acbca876SKumar Gala #ifdef CONFIG_PCI1 3734681457eSKumar Gala pci_speed = 66666000; 3744681457eSKumar Gala pci_32 = 1; 3754681457eSKumar Gala pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 3764681457eSKumar Gala pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 377acbca876SKumar Gala 3784681457eSKumar Gala if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 3794681457eSKumar Gala SET_STD_PCI_INFO(pci_info[num], 1); 3804681457eSKumar Gala pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 3814681457eSKumar Gala printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 382acbca876SKumar Gala (pci_32) ? 32 : 64, 383acbca876SKumar Gala (pci_speed == 33333000) ? "33" : 384acbca876SKumar Gala (pci_speed == 66666000) ? "66" : "unknown", 385acbca876SKumar Gala pci_clk_sel ? "sync" : "async", 386acbca876SKumar Gala pci_agent ? "agent" : "host", 3874681457eSKumar Gala pci_arb ? "arbiter" : "external-arbiter", 3884681457eSKumar Gala pci_info[num].regs); 389acbca876SKumar Gala 3904681457eSKumar Gala first_free_busno = fsl_pci_init_port(&pci_info[num++], 3914681457eSKumar Gala &pci1_hose, first_free_busno); 392acbca876SKumar Gala } else { 393acbca876SKumar Gala printf (" PCI: disabled\n"); 394acbca876SKumar Gala } 3954681457eSKumar Gala 3964681457eSKumar Gala puts("\n"); 397acbca876SKumar Gala #else 3984681457eSKumar Gala setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 399acbca876SKumar Gala #endif 400acbca876SKumar Gala 401acbca876SKumar Gala #ifdef CONFIG_PCIE1 4024681457eSKumar Gala pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 403acbca876SKumar Gala 4044681457eSKumar Gala if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 4054681457eSKumar Gala SET_STD_PCIE_INFO(pci_info[num], 1); 4064681457eSKumar Gala pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 4074681457eSKumar Gala printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", 40864917ca3SPeter Tyser pcie_ep ? "Endpoint" : "Root Complex", 4094681457eSKumar Gala pci_info[num].regs); 410acbca876SKumar Gala 4114681457eSKumar Gala first_free_busno = fsl_pci_init_port(&pci_info[num++], 4124681457eSKumar Gala &pcie1_hose, first_free_busno); 413acbca876SKumar Gala } else { 4144681457eSKumar Gala printf (" PCIE1: disabled\n"); 415acbca876SKumar Gala } 4164681457eSKumar Gala 4174681457eSKumar Gala puts("\n"); 418acbca876SKumar Gala #else 4194681457eSKumar Gala setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 420acbca876SKumar Gala #endif 421acbca876SKumar Gala } 422acbca876SKumar Gala #endif /* CONFIG_PCI */ 423acbca876SKumar Gala 424acbca876SKumar Gala #if defined(CONFIG_OF_BOARD_SETUP) 4252dba0deaSKumar Gala void ft_board_setup(void *blob, bd_t *bd) 4262dba0deaSKumar Gala { 427acbca876SKumar Gala ft_cpu_setup(blob, bd); 428acbca876SKumar Gala 429*6525d51fSKumar Gala FT_FSL_PCI_SETUP; 430acbca876SKumar Gala } 431acbca876SKumar Gala #endif 432