1acbca876SKumar Gala /* 26525d51fSKumar Gala * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. 3acbca876SKumar Gala * 4acbca876SKumar Gala * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5acbca876SKumar Gala * 6acbca876SKumar Gala * See file CREDITS for list of people who contributed to this 7acbca876SKumar Gala * project. 8acbca876SKumar Gala * 9acbca876SKumar Gala * This program is free software; you can redistribute it and/or 10acbca876SKumar Gala * modify it under the terms of the GNU General Public License as 11acbca876SKumar Gala * published by the Free Software Foundation; either version 2 of 12acbca876SKumar Gala * the License, or (at your option) any later version. 13acbca876SKumar Gala * 14acbca876SKumar Gala * This program is distributed in the hope that it will be useful, 15acbca876SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 16acbca876SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17acbca876SKumar Gala * GNU General Public License for more details. 18acbca876SKumar Gala * 19acbca876SKumar Gala * You should have received a copy of the GNU General Public License 20acbca876SKumar Gala * along with this program; if not, write to the Free Software 21acbca876SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22acbca876SKumar Gala * MA 02111-1307 USA 23acbca876SKumar Gala */ 24acbca876SKumar Gala 25acbca876SKumar Gala #include <common.h> 26acbca876SKumar Gala #include <pci.h> 27acbca876SKumar Gala #include <asm/processor.h> 28e6f5b35bSJon Loeliger #include <asm/mmu.h> 29acbca876SKumar Gala #include <asm/immap_85xx.h> 30c8514622SKumar Gala #include <asm/fsl_pci.h> 31e6f5b35bSJon Loeliger #include <asm/fsl_ddr_sdram.h> 32*5d27e02cSKumar Gala #include <asm/fsl_serdes.h> 33a30a549aSJon Loeliger #include <spd_sdram.h> 34acbca876SKumar Gala #include <i2c.h> 35acbca876SKumar Gala #include <ioports.h> 36acbca876SKumar Gala #include <libfdt.h> 37acbca876SKumar Gala #include <fdt_support.h> 38acbca876SKumar Gala 39acbca876SKumar Gala #include "bcsr.h" 40acbca876SKumar Gala 41acbca876SKumar Gala const qe_iop_conf_t qe_iop_conf_tab[] = { 42acbca876SKumar Gala /* GETH1 */ 43acbca876SKumar Gala {4, 10, 1, 0, 2}, /* TxD0 */ 44acbca876SKumar Gala {4, 9, 1, 0, 2}, /* TxD1 */ 45acbca876SKumar Gala {4, 8, 1, 0, 2}, /* TxD2 */ 46acbca876SKumar Gala {4, 7, 1, 0, 2}, /* TxD3 */ 47acbca876SKumar Gala {4, 23, 1, 0, 2}, /* TxD4 */ 48acbca876SKumar Gala {4, 22, 1, 0, 2}, /* TxD5 */ 49acbca876SKumar Gala {4, 21, 1, 0, 2}, /* TxD6 */ 50acbca876SKumar Gala {4, 20, 1, 0, 2}, /* TxD7 */ 51acbca876SKumar Gala {4, 15, 2, 0, 2}, /* RxD0 */ 52acbca876SKumar Gala {4, 14, 2, 0, 2}, /* RxD1 */ 53acbca876SKumar Gala {4, 13, 2, 0, 2}, /* RxD2 */ 54acbca876SKumar Gala {4, 12, 2, 0, 2}, /* RxD3 */ 55acbca876SKumar Gala {4, 29, 2, 0, 2}, /* RxD4 */ 56acbca876SKumar Gala {4, 28, 2, 0, 2}, /* RxD5 */ 57acbca876SKumar Gala {4, 27, 2, 0, 2}, /* RxD6 */ 58acbca876SKumar Gala {4, 26, 2, 0, 2}, /* RxD7 */ 59acbca876SKumar Gala {4, 11, 1, 0, 2}, /* TX_EN */ 60acbca876SKumar Gala {4, 24, 1, 0, 2}, /* TX_ER */ 61acbca876SKumar Gala {4, 16, 2, 0, 2}, /* RX_DV */ 62acbca876SKumar Gala {4, 30, 2, 0, 2}, /* RX_ER */ 63acbca876SKumar Gala {4, 17, 2, 0, 2}, /* RX_CLK */ 64acbca876SKumar Gala {4, 19, 1, 0, 2}, /* GTX_CLK */ 65acbca876SKumar Gala {1, 31, 2, 0, 3}, /* GTX125 */ 66acbca876SKumar Gala 67acbca876SKumar Gala /* GETH2 */ 68acbca876SKumar Gala {5, 10, 1, 0, 2}, /* TxD0 */ 69acbca876SKumar Gala {5, 9, 1, 0, 2}, /* TxD1 */ 70acbca876SKumar Gala {5, 8, 1, 0, 2}, /* TxD2 */ 71acbca876SKumar Gala {5, 7, 1, 0, 2}, /* TxD3 */ 72acbca876SKumar Gala {5, 23, 1, 0, 2}, /* TxD4 */ 73acbca876SKumar Gala {5, 22, 1, 0, 2}, /* TxD5 */ 74acbca876SKumar Gala {5, 21, 1, 0, 2}, /* TxD6 */ 75acbca876SKumar Gala {5, 20, 1, 0, 2}, /* TxD7 */ 76acbca876SKumar Gala {5, 15, 2, 0, 2}, /* RxD0 */ 77acbca876SKumar Gala {5, 14, 2, 0, 2}, /* RxD1 */ 78acbca876SKumar Gala {5, 13, 2, 0, 2}, /* RxD2 */ 79acbca876SKumar Gala {5, 12, 2, 0, 2}, /* RxD3 */ 80acbca876SKumar Gala {5, 29, 2, 0, 2}, /* RxD4 */ 81acbca876SKumar Gala {5, 28, 2, 0, 2}, /* RxD5 */ 82acbca876SKumar Gala {5, 27, 2, 0, 3}, /* RxD6 */ 83acbca876SKumar Gala {5, 26, 2, 0, 2}, /* RxD7 */ 84acbca876SKumar Gala {5, 11, 1, 0, 2}, /* TX_EN */ 85acbca876SKumar Gala {5, 24, 1, 0, 2}, /* TX_ER */ 86acbca876SKumar Gala {5, 16, 2, 0, 2}, /* RX_DV */ 87acbca876SKumar Gala {5, 30, 2, 0, 2}, /* RX_ER */ 88acbca876SKumar Gala {5, 17, 2, 0, 2}, /* RX_CLK */ 89acbca876SKumar Gala {5, 19, 1, 0, 2}, /* GTX_CLK */ 90acbca876SKumar Gala {1, 31, 2, 0, 3}, /* GTX125 */ 91acbca876SKumar Gala {4, 6, 3, 0, 2}, /* MDIO */ 92acbca876SKumar Gala {4, 5, 1, 0, 2}, /* MDC */ 9364d4bcb0SAnton Vorontsov 9464d4bcb0SAnton Vorontsov /* UART1 */ 9564d4bcb0SAnton Vorontsov {2, 0, 1, 0, 2}, /* UART_SOUT1 */ 9664d4bcb0SAnton Vorontsov {2, 1, 1, 0, 2}, /* UART_RTS1 */ 9764d4bcb0SAnton Vorontsov {2, 2, 2, 0, 2}, /* UART_CTS1 */ 9864d4bcb0SAnton Vorontsov {2, 3, 2, 0, 2}, /* UART_SIN1 */ 9964d4bcb0SAnton Vorontsov 100acbca876SKumar Gala {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 101acbca876SKumar Gala }; 102acbca876SKumar Gala 103acbca876SKumar Gala void local_bus_init(void); 104acbca876SKumar Gala void sdram_init(void); 105acbca876SKumar Gala 106acbca876SKumar Gala int board_early_init_f (void) 107acbca876SKumar Gala { 108acbca876SKumar Gala /* 109acbca876SKumar Gala * Initialize local bus. 110acbca876SKumar Gala */ 111acbca876SKumar Gala local_bus_init (); 112acbca876SKumar Gala 113acbca876SKumar Gala enable_8568mds_duart(); 114acbca876SKumar Gala enable_8568mds_flash_write(); 115ad162249SAnton Vorontsov #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 116ad162249SAnton Vorontsov reset_8568mds_uccs(); 117ad162249SAnton Vorontsov #endif 118acbca876SKumar Gala #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) 119acbca876SKumar Gala enable_8568mds_qe_mdio(); 120acbca876SKumar Gala #endif 121acbca876SKumar Gala 1226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_I2C2_OFFSET 123acbca876SKumar Gala /* Enable I2C2_SCL and I2C2_SDA */ 124acbca876SKumar Gala volatile struct par_io *port_c; 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140); 126acbca876SKumar Gala port_c->cpdir2 |= 0x0f000000; 127acbca876SKumar Gala port_c->cppar2 &= ~0x0f000000; 128acbca876SKumar Gala port_c->cppar2 |= 0x0a000000; 129acbca876SKumar Gala #endif 130acbca876SKumar Gala 131acbca876SKumar Gala return 0; 132acbca876SKumar Gala } 133acbca876SKumar Gala 134acbca876SKumar Gala int checkboard (void) 135acbca876SKumar Gala { 136acbca876SKumar Gala printf ("Board: 8568 MDS\n"); 137acbca876SKumar Gala 138acbca876SKumar Gala return 0; 139acbca876SKumar Gala } 140acbca876SKumar Gala 1419973e3c6SBecky Bruce phys_size_t 142acbca876SKumar Gala initdram(int board_type) 143acbca876SKumar Gala { 144acbca876SKumar Gala long dram_size = 0; 145acbca876SKumar Gala 146acbca876SKumar Gala puts("Initializing\n"); 147acbca876SKumar Gala 148acbca876SKumar Gala #if defined(CONFIG_DDR_DLL) 149acbca876SKumar Gala { 150acbca876SKumar Gala /* 151acbca876SKumar Gala * Work around to stabilize DDR DLL MSYNC_IN. 152acbca876SKumar Gala * Errata DDR9 seems to have been fixed. 153acbca876SKumar Gala * This is now the workaround for Errata DDR11: 154acbca876SKumar Gala * Override DLL = 1, Course Adj = 1, Tap Select = 0 155acbca876SKumar Gala */ 156acbca876SKumar Gala 1576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 158acbca876SKumar Gala 159acbca876SKumar Gala gur->ddrdllcr = 0x81000000; 160acbca876SKumar Gala asm("sync;isync;msync"); 161acbca876SKumar Gala udelay(200); 162acbca876SKumar Gala } 163acbca876SKumar Gala #endif 164e6f5b35bSJon Loeliger 165e6f5b35bSJon Loeliger dram_size = fsl_ddr_sdram(); 166e6f5b35bSJon Loeliger dram_size = setup_ddr_tlbs(dram_size / 0x100000); 167e6f5b35bSJon Loeliger dram_size *= 0x100000; 168acbca876SKumar Gala 169acbca876SKumar Gala /* 170acbca876SKumar Gala * SDRAM Initialization 171acbca876SKumar Gala */ 172acbca876SKumar Gala sdram_init(); 173acbca876SKumar Gala 174acbca876SKumar Gala puts(" DDR: "); 175acbca876SKumar Gala return dram_size; 176acbca876SKumar Gala } 177acbca876SKumar Gala 178acbca876SKumar Gala /* 179acbca876SKumar Gala * Initialize Local Bus 180acbca876SKumar Gala */ 181acbca876SKumar Gala void 182acbca876SKumar Gala local_bus_init(void) 183acbca876SKumar Gala { 1846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 185f51cdaf1SBecky Bruce volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 186acbca876SKumar Gala 187acbca876SKumar Gala uint clkdiv; 188acbca876SKumar Gala uint lbc_hz; 189acbca876SKumar Gala sys_info_t sysinfo; 190acbca876SKumar Gala 191acbca876SKumar Gala get_sys_info(&sysinfo); 192a5d212a2STrent Piepho clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 193acbca876SKumar Gala lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 194acbca876SKumar Gala 195acbca876SKumar Gala gur->lbiuiplldcr1 = 0x00078080; 196acbca876SKumar Gala if (clkdiv == 16) { 197acbca876SKumar Gala gur->lbiuiplldcr0 = 0x7c0f1bf0; 198acbca876SKumar Gala } else if (clkdiv == 8) { 199acbca876SKumar Gala gur->lbiuiplldcr0 = 0x6c0f1bf0; 200acbca876SKumar Gala } else if (clkdiv == 4) { 201acbca876SKumar Gala gur->lbiuiplldcr0 = 0x5c0f1bf0; 202acbca876SKumar Gala } 203acbca876SKumar Gala 204acbca876SKumar Gala lbc->lcrr |= 0x00030000; 205acbca876SKumar Gala 206acbca876SKumar Gala asm("sync;isync;msync"); 207acbca876SKumar Gala } 208acbca876SKumar Gala 209acbca876SKumar Gala /* 210acbca876SKumar Gala * Initialize SDRAM memory on the Local Bus. 211acbca876SKumar Gala */ 212acbca876SKumar Gala void 213acbca876SKumar Gala sdram_init(void) 214acbca876SKumar Gala { 2156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 216acbca876SKumar Gala 217acbca876SKumar Gala uint idx; 218f51cdaf1SBecky Bruce volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 2196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 220acbca876SKumar Gala uint lsdmr_common; 221acbca876SKumar Gala 222acbca876SKumar Gala puts(" SDRAM: "); 223acbca876SKumar Gala 2246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 225acbca876SKumar Gala 226acbca876SKumar Gala /* 227acbca876SKumar Gala * Setup SDRAM Base and Option Registers 228acbca876SKumar Gala */ 229f51cdaf1SBecky Bruce set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 230f51cdaf1SBecky Bruce set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 231acbca876SKumar Gala asm("msync"); 232acbca876SKumar Gala 2336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lbcr = CONFIG_SYS_LBC_LBCR; 234acbca876SKumar Gala asm("msync"); 235acbca876SKumar Gala 2366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lsrt = CONFIG_SYS_LBC_LSRT; 2376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 238acbca876SKumar Gala asm("msync"); 239acbca876SKumar Gala 240acbca876SKumar Gala /* 241acbca876SKumar Gala * MPC8568 uses "new" 15-16 style addressing. 242acbca876SKumar Gala */ 2436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 244b0fe93edSKumar Gala lsdmr_common |= LSDMR_BSMA1516; 245acbca876SKumar Gala 246acbca876SKumar Gala /* 247acbca876SKumar Gala * Issue PRECHARGE ALL command. 248acbca876SKumar Gala */ 249b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 250acbca876SKumar Gala asm("sync;msync"); 251acbca876SKumar Gala *sdram_addr = 0xff; 252acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 253acbca876SKumar Gala udelay(100); 254acbca876SKumar Gala 255acbca876SKumar Gala /* 256acbca876SKumar Gala * Issue 8 AUTO REFRESH commands. 257acbca876SKumar Gala */ 258acbca876SKumar Gala for (idx = 0; idx < 8; idx++) { 259b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 260acbca876SKumar Gala asm("sync;msync"); 261acbca876SKumar Gala *sdram_addr = 0xff; 262acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 263acbca876SKumar Gala udelay(100); 264acbca876SKumar Gala } 265acbca876SKumar Gala 266acbca876SKumar Gala /* 267acbca876SKumar Gala * Issue 8 MODE-set command. 268acbca876SKumar Gala */ 269b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 270acbca876SKumar Gala asm("sync;msync"); 271acbca876SKumar Gala *sdram_addr = 0xff; 272acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 273acbca876SKumar Gala udelay(100); 274acbca876SKumar Gala 275acbca876SKumar Gala /* 276acbca876SKumar Gala * Issue NORMAL OP command. 277acbca876SKumar Gala */ 278b0fe93edSKumar Gala lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 279acbca876SKumar Gala asm("sync;msync"); 280acbca876SKumar Gala *sdram_addr = 0xff; 281acbca876SKumar Gala ppcDcbf((unsigned long) sdram_addr); 282acbca876SKumar Gala udelay(200); /* Overkill. Must wait > 200 bus cycles */ 283acbca876SKumar Gala 284acbca876SKumar Gala #endif /* enable SDRAM init */ 285acbca876SKumar Gala } 286acbca876SKumar Gala 287acbca876SKumar Gala #if defined(CONFIG_PCI) 288acbca876SKumar Gala #ifndef CONFIG_PCI_PNP 289acbca876SKumar Gala static struct pci_config_table pci_mpc8568mds_config_table[] = { 290acbca876SKumar Gala { 291acbca876SKumar Gala PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 292acbca876SKumar Gala pci_cfgfunc_config_device, 293acbca876SKumar Gala {PCI_ENET0_IOADDR, 294acbca876SKumar Gala PCI_ENET0_MEMADDR, 295acbca876SKumar Gala PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} 296acbca876SKumar Gala }, 297acbca876SKumar Gala {} 298acbca876SKumar Gala }; 299acbca876SKumar Gala #endif 300acbca876SKumar Gala 301acbca876SKumar Gala static struct pci_controller pci1_hose = { 302acbca876SKumar Gala #ifndef CONFIG_PCI_PNP 303acbca876SKumar Gala config_table: pci_mpc8568mds_config_table, 304acbca876SKumar Gala #endif 305acbca876SKumar Gala }; 306acbca876SKumar Gala #endif /* CONFIG_PCI */ 307acbca876SKumar Gala 308acbca876SKumar Gala #ifdef CONFIG_PCIE1 309acbca876SKumar Gala static struct pci_controller pcie1_hose; 310acbca876SKumar Gala #endif /* CONFIG_PCIE1 */ 311acbca876SKumar Gala 312acbca876SKumar Gala /* 313acbca876SKumar Gala * pib_init() -- Initialize the PCA9555 IO expander on the PIB board 314acbca876SKumar Gala */ 315acbca876SKumar Gala void 316acbca876SKumar Gala pib_init(void) 317acbca876SKumar Gala { 318acbca876SKumar Gala u8 val8, orig_i2c_bus; 319acbca876SKumar Gala /* 320acbca876SKumar Gala * Assign PIB PMC2/3 to PCI bus 321acbca876SKumar Gala */ 322acbca876SKumar Gala 323acbca876SKumar Gala /*switch temporarily to I2C bus #2 */ 324acbca876SKumar Gala orig_i2c_bus = i2c_get_bus_num(); 325acbca876SKumar Gala i2c_set_bus_num(1); 326acbca876SKumar Gala 327acbca876SKumar Gala val8 = 0x00; 328acbca876SKumar Gala i2c_write(0x23, 0x6, 1, &val8, 1); 329acbca876SKumar Gala i2c_write(0x23, 0x7, 1, &val8, 1); 330acbca876SKumar Gala val8 = 0xff; 331acbca876SKumar Gala i2c_write(0x23, 0x2, 1, &val8, 1); 332acbca876SKumar Gala i2c_write(0x23, 0x3, 1, &val8, 1); 333acbca876SKumar Gala 334acbca876SKumar Gala val8 = 0x00; 335acbca876SKumar Gala i2c_write(0x26, 0x6, 1, &val8, 1); 336acbca876SKumar Gala val8 = 0x34; 337acbca876SKumar Gala i2c_write(0x26, 0x7, 1, &val8, 1); 338acbca876SKumar Gala val8 = 0xf9; 339acbca876SKumar Gala i2c_write(0x26, 0x2, 1, &val8, 1); 340acbca876SKumar Gala val8 = 0xff; 341acbca876SKumar Gala i2c_write(0x26, 0x3, 1, &val8, 1); 342acbca876SKumar Gala 343acbca876SKumar Gala val8 = 0x00; 344acbca876SKumar Gala i2c_write(0x27, 0x6, 1, &val8, 1); 345acbca876SKumar Gala i2c_write(0x27, 0x7, 1, &val8, 1); 346acbca876SKumar Gala val8 = 0xff; 347acbca876SKumar Gala i2c_write(0x27, 0x2, 1, &val8, 1); 348acbca876SKumar Gala val8 = 0xef; 349acbca876SKumar Gala i2c_write(0x27, 0x3, 1, &val8, 1); 350acbca876SKumar Gala 351acbca876SKumar Gala asm("eieio"); 352acbca876SKumar Gala } 353acbca876SKumar Gala 354acbca876SKumar Gala #ifdef CONFIG_PCI 3554681457eSKumar Gala void pci_init_board(void) 356acbca876SKumar Gala { 3576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 3584681457eSKumar Gala struct fsl_pci_info pci_info[2]; 3594681457eSKumar Gala u32 devdisr, pordevsr, io_sel; 3604681457eSKumar Gala u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 3614681457eSKumar Gala int first_free_busno = 0; 3624681457eSKumar Gala int num = 0; 3634681457eSKumar Gala 3644681457eSKumar Gala int pcie_ep, pcie_configured; 3654681457eSKumar Gala 3664681457eSKumar Gala devdisr = in_be32(&gur->devdisr); 3674681457eSKumar Gala pordevsr = in_be32(&gur->pordevsr); 3684681457eSKumar Gala porpllsr = in_be32(&gur->porpllsr); 3694681457eSKumar Gala io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 3704681457eSKumar Gala 3714681457eSKumar Gala debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 372acbca876SKumar Gala 373acbca876SKumar Gala #ifdef CONFIG_PCI1 3744681457eSKumar Gala pci_speed = 66666000; 3754681457eSKumar Gala pci_32 = 1; 3764681457eSKumar Gala pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 3774681457eSKumar Gala pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 378acbca876SKumar Gala 3794681457eSKumar Gala if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 3804681457eSKumar Gala SET_STD_PCI_INFO(pci_info[num], 1); 3814681457eSKumar Gala pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 3828ca78f2cSPeter Tyser printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 383acbca876SKumar Gala (pci_32) ? 32 : 64, 384acbca876SKumar Gala (pci_speed == 33333000) ? "33" : 385acbca876SKumar Gala (pci_speed == 66666000) ? "66" : "unknown", 386acbca876SKumar Gala pci_clk_sel ? "sync" : "async", 387acbca876SKumar Gala pci_agent ? "agent" : "host", 3884681457eSKumar Gala pci_arb ? "arbiter" : "external-arbiter", 3894681457eSKumar Gala pci_info[num].regs); 390acbca876SKumar Gala 3914681457eSKumar Gala first_free_busno = fsl_pci_init_port(&pci_info[num++], 3924681457eSKumar Gala &pci1_hose, first_free_busno); 393acbca876SKumar Gala } else { 394acbca876SKumar Gala printf("PCI: disabled\n"); 395acbca876SKumar Gala } 3964681457eSKumar Gala 3974681457eSKumar Gala puts("\n"); 398acbca876SKumar Gala #else 3994681457eSKumar Gala setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 400acbca876SKumar Gala #endif 401acbca876SKumar Gala 402acbca876SKumar Gala #ifdef CONFIG_PCIE1 403*5d27e02cSKumar Gala pcie_configured = is_serdes_configured(PCIE1); 404acbca876SKumar Gala 4054681457eSKumar Gala if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 4064681457eSKumar Gala SET_STD_PCIE_INFO(pci_info[num], 1); 4074681457eSKumar Gala pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 4088ca78f2cSPeter Tyser printf("PCIE1: connected to Slot as %s (base addr %lx)\n", 40964917ca3SPeter Tyser pcie_ep ? "Endpoint" : "Root Complex", 4104681457eSKumar Gala pci_info[num].regs); 411acbca876SKumar Gala 4124681457eSKumar Gala first_free_busno = fsl_pci_init_port(&pci_info[num++], 4134681457eSKumar Gala &pcie1_hose, first_free_busno); 414acbca876SKumar Gala } else { 4154681457eSKumar Gala printf("PCIE1: disabled\n"); 416acbca876SKumar Gala } 4174681457eSKumar Gala 4184681457eSKumar Gala puts("\n"); 419acbca876SKumar Gala #else 4204681457eSKumar Gala setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 421acbca876SKumar Gala #endif 422acbca876SKumar Gala } 423acbca876SKumar Gala #endif /* CONFIG_PCI */ 424acbca876SKumar Gala 425acbca876SKumar Gala #if defined(CONFIG_OF_BOARD_SETUP) 4262dba0deaSKumar Gala void ft_board_setup(void *blob, bd_t *bd) 4272dba0deaSKumar Gala { 428acbca876SKumar Gala ft_cpu_setup(blob, bd); 429acbca876SKumar Gala 4306525d51fSKumar Gala FT_FSL_PCI_SETUP; 431acbca876SKumar Gala } 432acbca876SKumar Gala #endif 433