1 /* 2 * Copyright 2007 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __BCSR_H_ 8 #define __BCSR_H_ 9 10 #include <common.h> 11 12 /* BCSR Bit definitions 13 * BCSR 0 * 14 0:3 ccb sys pll 15 4:6 cfg core pll 16 7 cfg boot seq 17 18 * BCSR 1 * 19 0:2 cfg rom lock 20 3:5 cfg host agent 21 6 PCI IO 22 7 cfg RIO size 23 24 * BCSR 2 * 25 0:4 QE PLL 26 5 QE clock 27 6 cfg PCI arbiter 28 29 * BCSR 3 * 30 0 TSEC1 reduce 31 1 TSEC2 reduce 32 2:3 TSEC1 protocol 33 4:5 TSEC2 protocol 34 6 PHY1 slave 35 7 PHY2 slave 36 37 * BCSR 4 * 38 4 clock enable 39 5 boot EPROM 40 6 GETH transactive reset 41 7 BRD write potect 42 43 * BCSR 5 * 44 1:3 Leds 1-3 45 4 UPC1 enable 46 5 UPC2 enable 47 6 UPC2 pos 48 7 RS232 enable 49 50 * BCSR 6 * 51 0 CFG ver 0 52 1 CFG ver 1 53 6 Register config led 54 7 Power on reset 55 56 * BCSR 7 * 57 2 board host mode indication 58 5 enable TSEC1 PHY 59 6 enable TSEC2 PHY 60 61 * BCSR 8 * 62 0 UCC GETH1 enable 63 1 UCC GMII enable 64 3 UCC TBI enable 65 5 UCC MII enable 66 7 Real time clock reset 67 68 * BCSR 9 * 69 0 UCC2 GETH enable 70 1 UCC2 GMII enable 71 3 UCC2 TBI enable 72 5 UCC2 MII enable 73 6 Ready only - indicate flash ready after burning 74 7 Flash write protect 75 */ 76 77 #define BCSR_UCC1_GETH_EN (0x1 << 7) 78 #define BCSR_UCC2_GETH_EN (0x1 << 7) 79 #define BCSR_UCC1_MODE_MSK (0x3 << 4) 80 #define BCSR_UCC2_MODE_MSK (0x3 << 0) 81 82 /*BCSR Utils functions*/ 83 84 void enable_8568mds_duart(void); 85 void enable_8568mds_flash_write(void); 86 void disable_8568mds_flash_write(void); 87 void enable_8568mds_qe_mdio(void); 88 89 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 90 void reset_8568mds_uccs(void); 91 #endif 92 93 #endif /* __BCSR_H_ */ 94