1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <pci.h> 25 #include <asm/processor.h> 26 #include <asm/immap_85xx.h> 27 #include <ioports.h> 28 #include <spd_sdram.h> 29 #include <libfdt.h> 30 #include <fdt_support.h> 31 32 #include "../common/cadmus.h" 33 #include "../common/eeprom.h" 34 #include "../common/via.h" 35 36 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 37 extern void ddr_enable_ecc(unsigned int dram_size); 38 #endif 39 40 void local_bus_init(void); 41 void sdram_init(void); 42 43 /* 44 * I/O Port configuration table 45 * 46 * if conf is 1, then that port pin will be configured at boot time 47 * according to the five values podr/pdir/ppar/psor/pdat for that entry 48 */ 49 50 const iop_conf_t iop_conf_tab[4][32] = { 51 52 /* Port A configuration */ 53 { /* conf ppar psor pdir podr pdat */ 54 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ 55 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ 56 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ 57 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ 58 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ 59 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ 60 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ 61 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ 62 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ 63 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ 64 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ 65 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ 66 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ 67 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ 68 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ 69 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ 70 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ 71 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ 72 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ 73 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ 74 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ 75 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ 76 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ 77 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ 78 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ 79 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ 80 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ 81 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ 82 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ 83 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ 84 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ 85 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ 86 }, 87 88 /* Port B configuration */ 89 { /* conf ppar psor pdir podr pdat */ 90 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ 91 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ 92 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ 93 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ 94 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ 95 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ 96 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ 97 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ 98 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ 99 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ 100 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ 101 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ 102 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ 103 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ 104 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ 105 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ 106 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ 107 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ 108 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ 109 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ 110 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 111 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 112 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 113 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 114 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 115 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 116 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 117 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 118 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 119 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 120 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 121 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ 122 }, 123 124 /* Port C */ 125 { /* conf ppar psor pdir podr pdat */ 126 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ 127 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ 128 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ 129 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ 130 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ 131 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ 132 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ 133 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ 134 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ 135 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ 136 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ 137 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ 138 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ 139 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ 140 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ 141 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ 142 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ 143 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ 144 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ 145 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ 146 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ 147 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ 148 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ 149 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ 150 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ 151 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ 152 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ 153 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ 154 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ 155 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ 156 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ 157 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ 158 }, 159 160 /* Port D */ 161 { /* conf ppar psor pdir podr pdat */ 162 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ 163 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ 164 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ 165 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ 166 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ 167 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ 168 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ 169 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ 170 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ 171 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ 172 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ 173 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ 174 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ 175 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ 176 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ 177 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ 178 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ 179 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ 180 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ 181 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ 182 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ 183 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ 184 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ 185 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ 186 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ 187 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ 188 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ 189 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ 190 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 191 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 192 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 193 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ 194 } 195 }; 196 197 int checkboard (void) 198 { 199 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 200 201 /* PCI slot in USER bits CSR[6:7] by convention. */ 202 uint pci_slot = get_pci_slot (); 203 204 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 205 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ 206 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ 207 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ 208 209 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 210 211 uint cpu_board_rev = get_cpu_board_revision (); 212 213 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", 214 get_board_version (), pci_slot); 215 216 printf ("CPU Board Revision %d.%d (0x%04x)\n", 217 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), 218 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); 219 220 printf (" PCI1: %d bit, %s MHz, %s\n", 221 (pci1_32) ? 32 : 64, 222 (pci1_speed == 33000000) ? "33" : 223 (pci1_speed == 66000000) ? "66" : "unknown", 224 pci1_clk_sel ? "sync" : "async"); 225 226 if (pci_dual) { 227 printf (" PCI2: 32 bit, 66 MHz, %s\n", 228 pci2_clk_sel ? "sync" : "async"); 229 } else { 230 printf (" PCI2: disabled\n"); 231 } 232 233 /* 234 * Initialize local bus. 235 */ 236 local_bus_init (); 237 238 return 0; 239 } 240 241 phys_size_t 242 initdram(int board_type) 243 { 244 long dram_size = 0; 245 246 puts("Initializing\n"); 247 248 #if defined(CONFIG_DDR_DLL) 249 { 250 /* 251 * Work around to stabilize DDR DLL MSYNC_IN. 252 * Errata DDR9 seems to have been fixed. 253 * This is now the workaround for Errata DDR11: 254 * Override DLL = 1, Course Adj = 1, Tap Select = 0 255 */ 256 257 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 258 259 gur->ddrdllcr = 0x81000000; 260 asm("sync;isync;msync"); 261 udelay(200); 262 } 263 #endif 264 dram_size = spd_sdram(); 265 266 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 267 /* 268 * Initialize and enable DDR ECC. 269 */ 270 ddr_enable_ecc(dram_size); 271 #endif 272 /* 273 * SDRAM Initialization 274 */ 275 sdram_init(); 276 277 puts(" DDR: "); 278 return dram_size; 279 } 280 281 /* 282 * Initialize Local Bus 283 */ 284 void 285 local_bus_init(void) 286 { 287 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 288 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 289 290 uint clkdiv; 291 uint lbc_hz; 292 sys_info_t sysinfo; 293 uint temp_lbcdll; 294 295 /* 296 * Errata LBC11. 297 * Fix Local Bus clock glitch when DLL is enabled. 298 * 299 * If localbus freq is < 66Mhz, DLL bypass mode must be used. 300 * If localbus freq is > 133Mhz, DLL can be safely enabled. 301 * Between 66 and 133, the DLL is enabled with an override workaround. 302 */ 303 304 get_sys_info(&sysinfo); 305 clkdiv = lbc->lcrr & 0x0f; 306 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 307 308 if (lbc_hz < 66) { 309 lbc->lcrr |= 0x80000000; /* DLL Bypass */ 310 311 } else if (lbc_hz >= 133) { 312 lbc->lcrr &= (~0x80000000); /* DLL Enabled */ 313 314 } else { 315 lbc->lcrr &= (~0x8000000); /* DLL Enabled */ 316 udelay(200); 317 318 /* 319 * Sample LBC DLL ctrl reg, upshift it to set the 320 * override bits. 321 */ 322 temp_lbcdll = gur->lbcdllcr; 323 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); 324 asm("sync;isync;msync"); 325 } 326 } 327 328 /* 329 * Initialize SDRAM memory on the Local Bus. 330 */ 331 void 332 sdram_init(void) 333 { 334 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) 335 336 uint idx; 337 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 338 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 339 uint cpu_board_rev; 340 uint lsdmr_common; 341 342 puts(" SDRAM: "); 343 344 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 345 346 /* 347 * Setup SDRAM Base and Option Registers 348 */ 349 lbc->or2 = CFG_OR2_PRELIM; 350 asm("msync"); 351 352 lbc->br2 = CFG_BR2_PRELIM; 353 asm("msync"); 354 355 lbc->lbcr = CFG_LBC_LBCR; 356 asm("msync"); 357 358 lbc->lsrt = CFG_LBC_LSRT; 359 lbc->mrtpr = CFG_LBC_MRTPR; 360 asm("msync"); 361 362 /* 363 * Determine which address lines to use baed on CPU board rev. 364 */ 365 cpu_board_rev = get_cpu_board_revision(); 366 lsdmr_common = CFG_LBC_LSDMR_COMMON; 367 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { 368 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; 369 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { 370 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; 371 } else { 372 /* 373 * Assume something unable to identify itself is 374 * really old, and likely has lines 16/17 mapped. 375 */ 376 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; 377 } 378 379 /* 380 * Issue PRECHARGE ALL command. 381 */ 382 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; 383 asm("sync;msync"); 384 *sdram_addr = 0xff; 385 ppcDcbf((unsigned long) sdram_addr); 386 udelay(100); 387 388 /* 389 * Issue 8 AUTO REFRESH commands. 390 */ 391 for (idx = 0; idx < 8; idx++) { 392 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; 393 asm("sync;msync"); 394 *sdram_addr = 0xff; 395 ppcDcbf((unsigned long) sdram_addr); 396 udelay(100); 397 } 398 399 /* 400 * Issue 8 MODE-set command. 401 */ 402 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; 403 asm("sync;msync"); 404 *sdram_addr = 0xff; 405 ppcDcbf((unsigned long) sdram_addr); 406 udelay(100); 407 408 /* 409 * Issue NORMAL OP command. 410 */ 411 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; 412 asm("sync;msync"); 413 *sdram_addr = 0xff; 414 ppcDcbf((unsigned long) sdram_addr); 415 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 416 417 #endif /* enable SDRAM init */ 418 } 419 420 #ifdef CONFIG_PCI 421 /* For some reason the Tundra PCI bridge shows up on itself as a 422 * different device. Work around that by refusing to configure it 423 */ 424 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 425 426 static struct pci_config_table pci_mpc85xxcds_config_table[] = { 427 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 428 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 429 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 430 mpc85xx_config_via_usbide, {0,0,0}}, 431 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 432 mpc85xx_config_via_usb, {0,0,0}}, 433 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 434 mpc85xx_config_via_usb2, {0,0,0}}, 435 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 436 mpc85xx_config_via_power, {0,0,0}}, 437 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 438 mpc85xx_config_via_ac97, {0,0,0}}, 439 {}, 440 }; 441 442 443 static struct pci_controller hose[] = { 444 { 445 config_table: pci_mpc85xxcds_config_table, 446 }, 447 #ifdef CONFIG_MPC85XX_PCI2 448 {}, 449 #endif 450 }; 451 452 #endif 453 454 void 455 pci_init_board(void) 456 { 457 #ifdef CONFIG_PCI 458 pci_mpc85xx_init(hose); 459 #endif 460 } 461 462 #if defined(CONFIG_OF_BOARD_SETUP) 463 void 464 ft_pci_setup(void *blob, bd_t *bd) 465 { 466 int node, tmp[2]; 467 const char *path; 468 469 node = fdt_path_offset(blob, "/aliases"); 470 tmp[0] = 0; 471 if (node >= 0) { 472 #ifdef CONFIG_PCI1 473 path = fdt_getprop(blob, node, "pci0", NULL); 474 if (path) { 475 tmp[1] = hose[0].last_busno - hose[0].first_busno; 476 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 477 } 478 #endif 479 #ifdef CONFIG_MPC85XX_PCI2 480 path = fdt_getprop(blob, node, "pci1", NULL); 481 if (path) { 482 tmp[1] = hose[1].last_busno - hose[1].first_busno; 483 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 484 } 485 #endif 486 } 487 } 488 #endif 489