1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <pci.h> 25 #include <asm/processor.h> 26 #include <asm/mmu.h> 27 #include <asm/immap_85xx.h> 28 #include <asm/fsl_ddr_sdram.h> 29 #include <ioports.h> 30 #include <spd_sdram.h> 31 #include <libfdt.h> 32 #include <fdt_support.h> 33 34 #include "../common/cadmus.h" 35 #include "../common/eeprom.h" 36 #include "../common/via.h" 37 38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 39 extern void ddr_enable_ecc(unsigned int dram_size); 40 #endif 41 42 void local_bus_init(void); 43 44 /* 45 * I/O Port configuration table 46 * 47 * if conf is 1, then that port pin will be configured at boot time 48 * according to the five values podr/pdir/ppar/psor/pdat for that entry 49 */ 50 51 const iop_conf_t iop_conf_tab[4][32] = { 52 53 /* Port A configuration */ 54 { /* conf ppar psor pdir podr pdat */ 55 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ 56 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ 57 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ 58 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ 59 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ 60 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ 61 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ 62 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ 63 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ 64 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ 65 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ 66 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ 67 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ 68 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ 69 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ 70 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ 71 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ 72 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ 73 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ 74 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ 75 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ 76 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ 77 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ 78 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ 79 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ 80 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ 81 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ 82 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ 83 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ 84 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ 85 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ 86 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ 87 }, 88 89 /* Port B configuration */ 90 { /* conf ppar psor pdir podr pdat */ 91 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ 92 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ 93 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ 94 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ 95 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ 96 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ 97 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ 98 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ 99 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ 100 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ 101 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ 102 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ 103 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ 104 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ 105 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ 106 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ 107 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ 108 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ 109 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ 110 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ 111 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 112 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 113 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 114 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 115 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 116 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 117 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 118 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 119 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 120 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 121 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 122 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ 123 }, 124 125 /* Port C */ 126 { /* conf ppar psor pdir podr pdat */ 127 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ 128 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ 129 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ 130 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ 131 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ 132 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ 133 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ 134 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ 135 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ 136 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ 137 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ 138 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ 139 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ 140 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ 141 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ 142 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ 143 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ 144 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ 145 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ 146 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ 147 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ 148 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ 149 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ 150 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ 151 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ 152 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ 153 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ 154 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ 155 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ 156 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ 157 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ 158 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ 159 }, 160 161 /* Port D */ 162 { /* conf ppar psor pdir podr pdat */ 163 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ 164 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ 165 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ 166 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ 167 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ 168 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ 169 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ 170 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ 171 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ 172 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ 173 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ 174 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ 175 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ 176 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ 177 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ 178 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ 179 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ 180 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ 181 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ 182 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ 183 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ 184 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ 185 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ 186 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ 187 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ 188 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ 189 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ 190 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ 191 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 192 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 193 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 194 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ 195 } 196 }; 197 198 int checkboard (void) 199 { 200 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 201 char buf[32]; 202 203 /* PCI slot in USER bits CSR[6:7] by convention. */ 204 uint pci_slot = get_pci_slot (); 205 206 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 207 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ 208 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ 209 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ 210 211 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 212 213 uint cpu_board_rev = get_cpu_board_revision (); 214 215 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", 216 get_board_version (), pci_slot); 217 218 printf ("CPU Board Revision %d.%d (0x%04x)\n", 219 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), 220 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); 221 222 printf("PCI1: %d bit, %s MHz, %s\n", 223 (pci1_32) ? 32 : 64, 224 strmhz(buf, pci1_speed), 225 pci1_clk_sel ? "sync" : "async"); 226 227 if (pci_dual) { 228 printf("PCI2: 32 bit, 66 MHz, %s\n", 229 pci2_clk_sel ? "sync" : "async"); 230 } else { 231 printf("PCI2: disabled\n"); 232 } 233 234 /* 235 * Initialize local bus. 236 */ 237 local_bus_init (); 238 239 return 0; 240 } 241 242 /* 243 * Initialize Local Bus 244 */ 245 void 246 local_bus_init(void) 247 { 248 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 249 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 250 251 uint clkdiv; 252 uint lbc_hz; 253 sys_info_t sysinfo; 254 uint temp_lbcdll; 255 256 /* 257 * Errata LBC11. 258 * Fix Local Bus clock glitch when DLL is enabled. 259 * 260 * If localbus freq is < 66MHz, DLL bypass mode must be used. 261 * If localbus freq is > 133MHz, DLL can be safely enabled. 262 * Between 66 and 133, the DLL is enabled with an override workaround. 263 */ 264 265 get_sys_info(&sysinfo); 266 clkdiv = lbc->lcrr & LCRR_CLKDIV; 267 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 268 269 if (lbc_hz < 66) { 270 lbc->lcrr |= 0x80000000; /* DLL Bypass */ 271 272 } else if (lbc_hz >= 133) { 273 lbc->lcrr &= (~0x80000000); /* DLL Enabled */ 274 275 } else { 276 lbc->lcrr &= (~0x80000000); /* DLL Enabled */ 277 udelay(200); 278 279 /* 280 * Sample LBC DLL ctrl reg, upshift it to set the 281 * override bits. 282 */ 283 temp_lbcdll = gur->lbcdllcr; 284 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); 285 asm("sync;isync;msync"); 286 } 287 } 288 289 /* 290 * Initialize SDRAM memory on the Local Bus. 291 */ 292 void lbc_sdram_init(void) 293 { 294 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 295 296 uint idx; 297 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 298 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 299 uint cpu_board_rev; 300 uint lsdmr_common; 301 302 puts("LBC SDRAM: "); 303 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, 304 "\n "); 305 306 /* 307 * Setup SDRAM Base and Option Registers 308 */ 309 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 310 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 311 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 312 asm("msync"); 313 314 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 315 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 316 asm("msync"); 317 318 /* 319 * Determine which address lines to use baed on CPU board rev. 320 */ 321 cpu_board_rev = get_cpu_board_revision(); 322 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 323 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { 324 lsdmr_common |= LSDMR_BSMA1617; 325 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { 326 lsdmr_common |= LSDMR_BSMA1516; 327 } else { 328 /* 329 * Assume something unable to identify itself is 330 * really old, and likely has lines 16/17 mapped. 331 */ 332 lsdmr_common |= LSDMR_BSMA1617; 333 } 334 335 /* 336 * Issue PRECHARGE ALL command. 337 */ 338 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 339 asm("sync;msync"); 340 *sdram_addr = 0xff; 341 ppcDcbf((unsigned long) sdram_addr); 342 udelay(100); 343 344 /* 345 * Issue 8 AUTO REFRESH commands. 346 */ 347 for (idx = 0; idx < 8; idx++) { 348 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 349 asm("sync;msync"); 350 *sdram_addr = 0xff; 351 ppcDcbf((unsigned long) sdram_addr); 352 udelay(100); 353 } 354 355 /* 356 * Issue 8 MODE-set command. 357 */ 358 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 359 asm("sync;msync"); 360 *sdram_addr = 0xff; 361 ppcDcbf((unsigned long) sdram_addr); 362 udelay(100); 363 364 /* 365 * Issue NORMAL OP command. 366 */ 367 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 368 asm("sync;msync"); 369 *sdram_addr = 0xff; 370 ppcDcbf((unsigned long) sdram_addr); 371 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 372 373 #endif /* enable SDRAM init */ 374 } 375 376 #ifdef CONFIG_PCI 377 /* For some reason the Tundra PCI bridge shows up on itself as a 378 * different device. Work around that by refusing to configure it 379 */ 380 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 381 382 static struct pci_config_table pci_mpc85xxcds_config_table[] = { 383 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 384 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 385 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 386 mpc85xx_config_via_usbide, {0,0,0}}, 387 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 388 mpc85xx_config_via_usb, {0,0,0}}, 389 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 390 mpc85xx_config_via_usb2, {0,0,0}}, 391 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 392 mpc85xx_config_via_power, {0,0,0}}, 393 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 394 mpc85xx_config_via_ac97, {0,0,0}}, 395 {}, 396 }; 397 398 399 static struct pci_controller hose[] = { 400 { 401 config_table: pci_mpc85xxcds_config_table, 402 }, 403 #ifdef CONFIG_MPC85XX_PCI2 404 {}, 405 #endif 406 }; 407 408 #endif 409 410 void 411 pci_init_board(void) 412 { 413 #ifdef CONFIG_PCI 414 pci_mpc85xx_init(hose); 415 #endif 416 } 417 418 #if defined(CONFIG_OF_BOARD_SETUP) 419 void 420 ft_pci_setup(void *blob, bd_t *bd) 421 { 422 int node, tmp[2]; 423 const char *path; 424 425 node = fdt_path_offset(blob, "/aliases"); 426 tmp[0] = 0; 427 if (node >= 0) { 428 #ifdef CONFIG_PCI1 429 path = fdt_getprop(blob, node, "pci0", NULL); 430 if (path) { 431 tmp[1] = hose[0].last_busno - hose[0].first_busno; 432 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 433 } 434 #endif 435 #ifdef CONFIG_MPC85XX_PCI2 436 path = fdt_getprop(blob, node, "pci1", NULL); 437 if (path) { 438 tmp[1] = hose[1].last_busno - hose[1].first_busno; 439 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 440 } 441 #endif 442 } 443 } 444 #endif 445