1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2004, 2011 Freescale Semiconductor.
4  */
5 
6 #include <common.h>
7 #include <pci.h>
8 #include <asm/processor.h>
9 #include <asm/mmu.h>
10 #include <asm/immap_85xx.h>
11 #include <fsl_ddr_sdram.h>
12 #include <ioports.h>
13 #include <spd_sdram.h>
14 #include <linux/libfdt.h>
15 #include <fdt_support.h>
16 
17 #include "../common/cadmus.h"
18 #include "../common/eeprom.h"
19 #include "../common/via.h"
20 
21 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
22 extern void ddr_enable_ecc(unsigned int dram_size);
23 #endif
24 
25 void local_bus_init(void);
26 
27 /*
28  * I/O Port configuration table
29  *
30  * if conf is 1, then that port pin will be configured at boot time
31  * according to the five values podr/pdir/ppar/psor/pdat for that entry
32  */
33 
34 const iop_conf_t iop_conf_tab[4][32] = {
35 
36     /* Port A configuration */
37     {   /*            conf ppar psor pdir podr pdat */
38 	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
39 	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
40 	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
41 	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
42 	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
43 	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
44 	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
45 	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
46 	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
47 	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
48 	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
49 	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
50 	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
51 	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
52 	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
53 	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
54 	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
55 	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
56 	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
57 	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
58 	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
59 	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
60 	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
61 	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
62 	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
63 	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
64 	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
65 	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
66 	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
67 	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
68 	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
69 	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
70     },
71 
72     /* Port B configuration */
73     {   /*            conf ppar psor pdir podr pdat */
74 	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
75 	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
76 	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
77 	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
78 	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
79 	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
80 	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
81 	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
82 	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
83 	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
84 	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
85 	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
86 	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
87 	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
88 	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
89 	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
90 	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
91 	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
92 	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
93 	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
94 	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
95 	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
96 	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
97 	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
98 	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
99 	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
100 	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
101 	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
102 	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
103 	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
104 	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
105 	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
106     },
107 
108     /* Port C */
109     {   /*            conf ppar psor pdir podr pdat */
110 	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
111 	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
112 	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
113 	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
114 	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
115 	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
116 	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
117 	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
118 	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
119 	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
120 	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
121 	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
122 	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
123 	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
124 	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
125 	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
126 	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
127 	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
128 	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
129 	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
130 	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
131 	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
132 	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
133 	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
134 	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
135 	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
136 	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
137 	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
138 	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
139 	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
140 	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
141 	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
142     },
143 
144     /* Port D */
145     {   /*            conf ppar psor pdir podr pdat */
146 	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
147 	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
148 	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
149 	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
150 	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
151 	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
152 	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
153 	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
154 	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
155 	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
156 	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
157 	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
158 	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
159 	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
160 	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
161 	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
162 	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
163 	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
164 	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
165 	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
166 	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
167 	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
168 	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
169 	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
170 	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
171 	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
172 	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
173 	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
174 	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
175 	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
176 	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
177 	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
178     }
179 };
180 
181 int checkboard (void)
182 {
183 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
184 	char buf[32];
185 
186 	/* PCI slot in USER bits CSR[6:7] by convention. */
187 	uint pci_slot = get_pci_slot ();
188 
189 	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
190 	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
191 	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
192 	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
193 
194 	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
195 
196 	uint cpu_board_rev = get_cpu_board_revision ();
197 
198 	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
199 		get_board_version (), pci_slot);
200 
201 	printf ("CPU Board Revision %d.%d (0x%04x)\n",
202 		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
203 		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
204 
205 	printf("PCI1: %d bit, %s MHz, %s\n",
206 		(pci1_32) ? 32 : 64,
207 		strmhz(buf, pci1_speed),
208 		pci1_clk_sel ? "sync" : "async");
209 
210 	if (pci_dual) {
211 		printf("PCI2: 32 bit, 66 MHz, %s\n",
212 			pci2_clk_sel ? "sync" : "async");
213 	} else {
214 		printf("PCI2: disabled\n");
215 	}
216 
217 	/*
218 	 * Initialize local bus.
219 	 */
220 	local_bus_init ();
221 
222 	return 0;
223 }
224 
225 /*
226  * Initialize Local Bus
227  */
228 void
229 local_bus_init(void)
230 {
231 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
232 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
233 
234 	uint clkdiv;
235 	uint lbc_hz;
236 	sys_info_t sysinfo;
237 	uint temp_lbcdll;
238 
239 	/*
240 	 * Errata LBC11.
241 	 * Fix Local Bus clock glitch when DLL is enabled.
242 	 *
243 	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
244 	 * If localbus freq is > 133MHz, DLL can be safely enabled.
245 	 * Between 66 and 133, the DLL is enabled with an override workaround.
246 	 */
247 
248 	get_sys_info(&sysinfo);
249 	clkdiv = lbc->lcrr & LCRR_CLKDIV;
250 	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
251 
252 	if (lbc_hz < 66) {
253 		lbc->lcrr |= LCRR_DBYP;	/* DLL Bypass */
254 
255 	} else if (lbc_hz >= 133) {
256 		lbc->lcrr &= (~LCRR_DBYP);		/* DLL Enabled */
257 
258 	} else {
259 		lbc->lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
260 		udelay(200);
261 
262 		/*
263 		 * Sample LBC DLL ctrl reg, upshift it to set the
264 		 * override bits.
265 		 */
266 		temp_lbcdll = gur->lbcdllcr;
267 		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
268 		asm("sync;isync;msync");
269 	}
270 }
271 
272 /*
273  * Initialize SDRAM memory on the Local Bus.
274  */
275 void lbc_sdram_init(void)
276 {
277 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
278 
279 	uint idx;
280 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
281 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
282 	uint cpu_board_rev;
283 	uint lsdmr_common;
284 
285 	puts("LBC SDRAM: ");
286 	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
287 		   "\n       ");
288 
289 	/*
290 	 * Setup SDRAM Base and Option Registers
291 	 */
292 	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
293 	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
294 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
295 	asm("msync");
296 
297 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
298 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
299 	asm("msync");
300 
301 	/*
302 	 * Determine which address lines to use baed on CPU board rev.
303 	 */
304 	cpu_board_rev = get_cpu_board_revision();
305 	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
306 	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
307 		lsdmr_common |= LSDMR_BSMA1617;
308 	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
309 		lsdmr_common |= LSDMR_BSMA1516;
310 	} else {
311 		/*
312 		 * Assume something unable to identify itself is
313 		 * really old, and likely has lines 16/17 mapped.
314 		 */
315 		lsdmr_common |= LSDMR_BSMA1617;
316 	}
317 
318 	/*
319 	 * Issue PRECHARGE ALL command.
320 	 */
321 	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
322 	asm("sync;msync");
323 	*sdram_addr = 0xff;
324 	ppcDcbf((unsigned long) sdram_addr);
325 	udelay(100);
326 
327 	/*
328 	 * Issue 8 AUTO REFRESH commands.
329 	 */
330 	for (idx = 0; idx < 8; idx++) {
331 		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
332 		asm("sync;msync");
333 		*sdram_addr = 0xff;
334 		ppcDcbf((unsigned long) sdram_addr);
335 		udelay(100);
336 	}
337 
338 	/*
339 	 * Issue 8 MODE-set command.
340 	 */
341 	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
342 	asm("sync;msync");
343 	*sdram_addr = 0xff;
344 	ppcDcbf((unsigned long) sdram_addr);
345 	udelay(100);
346 
347 	/*
348 	 * Issue NORMAL OP command.
349 	 */
350 	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
351 	asm("sync;msync");
352 	*sdram_addr = 0xff;
353 	ppcDcbf((unsigned long) sdram_addr);
354 	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
355 
356 #endif	/* enable SDRAM init */
357 }
358 
359 #ifdef CONFIG_PCI
360 /* For some reason the Tundra PCI bridge shows up on itself as a
361  * different device.  Work around that by refusing to configure it
362  */
363 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
364 
365 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
366 	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
367 	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
368 	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
369 		mpc85xx_config_via_usbide, {0,0,0}},
370 	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
371 		mpc85xx_config_via_usb, {0,0,0}},
372 	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
373 		mpc85xx_config_via_usb2, {0,0,0}},
374 	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
375 		mpc85xx_config_via_power, {0,0,0}},
376 	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
377 		mpc85xx_config_via_ac97, {0,0,0}},
378 	{},
379 };
380 
381 
382 static struct pci_controller hose[] = {
383 	{
384 	config_table: pci_mpc85xxcds_config_table,
385 	},
386 #ifdef CONFIG_MPC85XX_PCI2
387 	{},
388 #endif
389 };
390 
391 #endif
392 
393 void
394 pci_init_board(void)
395 {
396 #ifdef CONFIG_PCI
397 	pci_mpc85xx_init(hose);
398 #endif
399 }
400 
401 #if defined(CONFIG_OF_BOARD_SETUP)
402 void
403 ft_pci_setup(void *blob, bd_t *bd)
404 {
405 	int node, tmp[2];
406 	const char *path;
407 
408 	node = fdt_path_offset(blob, "/aliases");
409 	tmp[0] = 0;
410 	if (node >= 0) {
411 #ifdef CONFIG_PCI1
412 		path = fdt_getprop(blob, node, "pci0", NULL);
413 		if (path) {
414 			tmp[1] = hose[0].last_busno - hose[0].first_busno;
415 			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
416 		}
417 #endif
418 #ifdef CONFIG_MPC85XX_PCI2
419 		path = fdt_getprop(blob, node, "pci1", NULL);
420 		if (path) {
421 			tmp[1] = hose[1].last_busno - hose[1].first_busno;
422 			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
423 		}
424 #endif
425 	}
426 }
427 #endif
428