1 /* 2 * Copyright 2008, 2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <asm/mmu.h> 28 29 struct fsl_e_tlb_entry tlb_table[] = { 30 /* TLB 0 - for temp stack in cache */ 31 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 32 MAS3_SX|MAS3_SW|MAS3_SR, 0, 33 0, 0, BOOKE_PAGESZ_4K, 0), 34 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 35 MAS3_SX|MAS3_SW|MAS3_SR, 0, 36 0, 0, BOOKE_PAGESZ_4K, 0), 37 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 38 MAS3_SX|MAS3_SW|MAS3_SR, 0, 39 0, 0, BOOKE_PAGESZ_4K, 0), 40 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 41 MAS3_SX|MAS3_SW|MAS3_SR, 0, 42 0, 0, BOOKE_PAGESZ_4K, 0), 43 44 /* TLB 1 */ 45 /* 46 * Entry 0: 47 * FLASH(cover boot page) 16M Non-cacheable, guarded 48 */ 49 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51 0, 0, BOOKE_PAGESZ_16M, 1), 52 53 /* 54 * Entry 1: 55 * CCSRBAR 1M Non-cacheable, guarded 56 */ 57 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 59 0, 1, BOOKE_PAGESZ_1M, 1), 60 61 /* 62 * Entry 2: 63 * LBC SDRAM 64M Cacheable, non-guarded 64 */ 65 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, 66 CONFIG_SYS_LBC_SDRAM_BASE_PHYS, 67 MAS3_SX|MAS3_SW|MAS3_SR, 0, 68 0, 2, BOOKE_PAGESZ_64M, 1), 69 70 /* 71 * Entry 3: 72 * CADMUS registers 1M Non-cacheable, guarded 73 */ 74 SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS, 75 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 76 0, 3, BOOKE_PAGESZ_1M, 1), 77 78 /* 79 * Entry 4: 80 * PCI and PCIe MEM 1G Non-cacheable, guarded 81 */ 82 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, 83 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 84 0, 4, BOOKE_PAGESZ_1G, 1), 85 86 /* 87 * Entry 5: 88 * PCI1 IO 1M Non-cacheable, guarded 89 */ 90 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, 91 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 92 0, 5, BOOKE_PAGESZ_1M, 1), 93 94 /* 95 * Entry 6: 96 * PCIe IO 1M Non-cacheable, guarded 97 */ 98 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 99 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 100 0, 6, BOOKE_PAGESZ_1M, 1), 101 }; 102 103 int num_tlb_entries = ARRAY_SIZE(tlb_table); 104