10db37dc2SKumar Gala /* 28b47d7ecSKumar Gala * Copyright 2008, 2011 Freescale Semiconductor, Inc. 30db37dc2SKumar Gala * 40db37dc2SKumar Gala * (C) Copyright 2000 50db37dc2SKumar Gala * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 60db37dc2SKumar Gala * 70db37dc2SKumar Gala * See file CREDITS for list of people who contributed to this 80db37dc2SKumar Gala * project. 90db37dc2SKumar Gala * 100db37dc2SKumar Gala * This program is free software; you can redistribute it and/or 110db37dc2SKumar Gala * modify it under the terms of the GNU General Public License as 120db37dc2SKumar Gala * published by the Free Software Foundation; either version 2 of 130db37dc2SKumar Gala * the License, or (at your option) any later version. 140db37dc2SKumar Gala * 150db37dc2SKumar Gala * This program is distributed in the hope that it will be useful, 160db37dc2SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 170db37dc2SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 180db37dc2SKumar Gala * GNU General Public License for more details. 190db37dc2SKumar Gala * 200db37dc2SKumar Gala * You should have received a copy of the GNU General Public License 210db37dc2SKumar Gala * along with this program; if not, write to the Free Software 220db37dc2SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 230db37dc2SKumar Gala * MA 02111-1307 USA 240db37dc2SKumar Gala */ 250db37dc2SKumar Gala 260db37dc2SKumar Gala #include <common.h> 270db37dc2SKumar Gala #include <asm/mmu.h> 280db37dc2SKumar Gala 290db37dc2SKumar Gala struct fsl_e_tlb_entry tlb_table[] = { 300db37dc2SKumar Gala /* TLB 0 - for temp stack in cache */ 316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 320db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, 0, 330db37dc2SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 350db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, 0, 360db37dc2SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 380db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, 0, 390db37dc2SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 410db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, 0, 420db37dc2SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 430db37dc2SKumar Gala 44*fff80975Schenhui zhao /* TLB 1 */ 450db37dc2SKumar Gala /* 46*fff80975Schenhui zhao * Entry 0: 47*fff80975Schenhui zhao * FLASH(cover boot page) 16M Non-cacheable, guarded 480db37dc2SKumar Gala */ 49*fff80975Schenhui zhao SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 500db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 510db37dc2SKumar Gala 0, 0, BOOKE_PAGESZ_16M, 1), 520db37dc2SKumar Gala 530db37dc2SKumar Gala /* 54*fff80975Schenhui zhao * Entry 1: 55*fff80975Schenhui zhao * CCSRBAR 1M Non-cacheable, guarded 560db37dc2SKumar Gala */ 576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 580db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 59*fff80975Schenhui zhao 0, 1, BOOKE_PAGESZ_1M, 1), 600db37dc2SKumar Gala 610db37dc2SKumar Gala /* 62*fff80975Schenhui zhao * Entry 2: 63*fff80975Schenhui zhao * LBC SDRAM 64M Cacheable, non-guarded 640db37dc2SKumar Gala */ 65*fff80975Schenhui zhao SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, 66*fff80975Schenhui zhao CONFIG_SYS_LBC_SDRAM_BASE_PHYS, 670db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, 0, 68*fff80975Schenhui zhao 0, 2, BOOKE_PAGESZ_64M, 1), 690db37dc2SKumar Gala 700db37dc2SKumar Gala /* 71*fff80975Schenhui zhao * Entry 3: 72*fff80975Schenhui zhao * CADMUS registers 1M Non-cacheable, guarded 730db37dc2SKumar Gala */ 74*fff80975Schenhui zhao SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS, 750db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 76*fff80975Schenhui zhao 0, 3, BOOKE_PAGESZ_1M, 1), 77*fff80975Schenhui zhao 78*fff80975Schenhui zhao /* 79*fff80975Schenhui zhao * Entry 4: 80*fff80975Schenhui zhao * PCI and PCIe MEM 1G Non-cacheable, guarded 81*fff80975Schenhui zhao */ 82*fff80975Schenhui zhao SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, 83*fff80975Schenhui zhao MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 84*fff80975Schenhui zhao 0, 4, BOOKE_PAGESZ_1G, 1), 85*fff80975Schenhui zhao 86*fff80975Schenhui zhao /* 87*fff80975Schenhui zhao * Entry 5: 88*fff80975Schenhui zhao * PCI1 IO 1M Non-cacheable, guarded 89*fff80975Schenhui zhao */ 90*fff80975Schenhui zhao SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, 91*fff80975Schenhui zhao MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 92*fff80975Schenhui zhao 0, 5, BOOKE_PAGESZ_1M, 1), 93*fff80975Schenhui zhao 94*fff80975Schenhui zhao /* 95*fff80975Schenhui zhao * Entry 6: 96*fff80975Schenhui zhao * PCIe IO 1M Non-cacheable, guarded 97*fff80975Schenhui zhao */ 98*fff80975Schenhui zhao SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 99*fff80975Schenhui zhao MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 100*fff80975Schenhui zhao 0, 6, BOOKE_PAGESZ_1M, 1), 1010db37dc2SKumar Gala }; 1020db37dc2SKumar Gala 1030db37dc2SKumar Gala int num_tlb_entries = ARRAY_SIZE(tlb_table); 104