1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 20db37dc2SKumar Gala /* 38b47d7ecSKumar Gala * Copyright 2008, 2011 Freescale Semiconductor, Inc. 40db37dc2SKumar Gala * 50db37dc2SKumar Gala * (C) Copyright 2000 60db37dc2SKumar Gala * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 70db37dc2SKumar Gala */ 80db37dc2SKumar Gala 90db37dc2SKumar Gala #include <common.h> 100db37dc2SKumar Gala #include <asm/mmu.h> 110db37dc2SKumar Gala 120db37dc2SKumar Gala struct fsl_e_tlb_entry tlb_table[] = { 130db37dc2SKumar Gala /* TLB 0 - for temp stack in cache */ 146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 150db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, 0, 160db37dc2SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 180db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, 0, 190db37dc2SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 210db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, 0, 220db37dc2SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 240db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, 0, 250db37dc2SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 260db37dc2SKumar Gala 27fff80975Schenhui zhao /* TLB 1 */ 280db37dc2SKumar Gala /* 29fff80975Schenhui zhao * Entry 0: 30fff80975Schenhui zhao * FLASH(cover boot page) 16M Non-cacheable, guarded 310db37dc2SKumar Gala */ 32fff80975Schenhui zhao SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 330db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 340db37dc2SKumar Gala 0, 0, BOOKE_PAGESZ_16M, 1), 350db37dc2SKumar Gala 360db37dc2SKumar Gala /* 37fff80975Schenhui zhao * Entry 1: 38fff80975Schenhui zhao * CCSRBAR 1M Non-cacheable, guarded 390db37dc2SKumar Gala */ 406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 410db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 42fff80975Schenhui zhao 0, 1, BOOKE_PAGESZ_1M, 1), 430db37dc2SKumar Gala 440db37dc2SKumar Gala /* 45fff80975Schenhui zhao * Entry 2: 46fff80975Schenhui zhao * LBC SDRAM 64M Cacheable, non-guarded 470db37dc2SKumar Gala */ 48fff80975Schenhui zhao SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, 49fff80975Schenhui zhao CONFIG_SYS_LBC_SDRAM_BASE_PHYS, 50316f0d0fSYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 51fff80975Schenhui zhao 0, 2, BOOKE_PAGESZ_64M, 1), 520db37dc2SKumar Gala 530db37dc2SKumar Gala /* 54fff80975Schenhui zhao * Entry 3: 55fff80975Schenhui zhao * CADMUS registers 1M Non-cacheable, guarded 560db37dc2SKumar Gala */ 57fff80975Schenhui zhao SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS, 580db37dc2SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 59fff80975Schenhui zhao 0, 3, BOOKE_PAGESZ_1M, 1), 60fff80975Schenhui zhao 61fff80975Schenhui zhao /* 62fff80975Schenhui zhao * Entry 4: 63fff80975Schenhui zhao * PCI and PCIe MEM 1G Non-cacheable, guarded 64fff80975Schenhui zhao */ 65fff80975Schenhui zhao SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, 66fff80975Schenhui zhao MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67fff80975Schenhui zhao 0, 4, BOOKE_PAGESZ_1G, 1), 68fff80975Schenhui zhao 69fff80975Schenhui zhao /* 70fff80975Schenhui zhao * Entry 5: 71fff80975Schenhui zhao * PCI1 IO 1M Non-cacheable, guarded 72fff80975Schenhui zhao */ 73fff80975Schenhui zhao SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, 74fff80975Schenhui zhao MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 75fff80975Schenhui zhao 0, 5, BOOKE_PAGESZ_1M, 1), 76fff80975Schenhui zhao 77fff80975Schenhui zhao /* 78fff80975Schenhui zhao * Entry 6: 79fff80975Schenhui zhao * PCIe IO 1M Non-cacheable, guarded 80fff80975Schenhui zhao */ 81fff80975Schenhui zhao SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 82fff80975Schenhui zhao MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 83fff80975Schenhui zhao 0, 6, BOOKE_PAGESZ_1M, 1), 840db37dc2SKumar Gala }; 850db37dc2SKumar Gala 860db37dc2SKumar Gala int num_tlb_entries = ARRAY_SIZE(tlb_table); 87