1 /* 2 * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/mmu.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/fsl_serdes.h> 33 #include <miiphy.h> 34 #include <libfdt.h> 35 #include <fdt_support.h> 36 #include <tsec.h> 37 #include <fsl_mdio.h> 38 #include <netdev.h> 39 40 #include "../common/cadmus.h" 41 #include "../common/eeprom.h" 42 #include "../common/via.h" 43 44 void local_bus_init(void); 45 46 int checkboard (void) 47 { 48 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 49 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 50 51 /* PCI slot in USER bits CSR[6:7] by convention. */ 52 uint pci_slot = get_pci_slot (); 53 54 uint cpu_board_rev = get_cpu_board_revision (); 55 56 puts("Board: MPC8548CDS"); 57 printf(" Carrier Rev: 0x%02x, PCI Slot %d\n", 58 get_board_version(), pci_slot); 59 printf(" Daughtercard Rev: %d.%d (0x%04x)\n", 60 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), 61 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); 62 /* 63 * Initialize local bus. 64 */ 65 local_bus_init (); 66 67 /* 68 * Hack TSEC 3 and 4 IO voltages. 69 */ 70 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ 71 72 ecm->eedr = 0xffffffff; /* clear ecm errors */ 73 ecm->eeer = 0xffffffff; /* enable ecm errors */ 74 return 0; 75 } 76 77 /* 78 * Initialize Local Bus 79 */ 80 void 81 local_bus_init(void) 82 { 83 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 84 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 85 86 uint clkdiv; 87 sys_info_t sysinfo; 88 89 get_sys_info(&sysinfo); 90 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 91 92 gur->lbiuiplldcr1 = 0x00078080; 93 if (clkdiv == 16) { 94 gur->lbiuiplldcr0 = 0x7c0f1bf0; 95 } else if (clkdiv == 8) { 96 gur->lbiuiplldcr0 = 0x6c0f1bf0; 97 } else if (clkdiv == 4) { 98 gur->lbiuiplldcr0 = 0x5c0f1bf0; 99 } 100 101 lbc->lcrr |= 0x00030000; 102 103 asm("sync;isync;msync"); 104 105 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 106 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 107 } 108 109 /* 110 * Initialize SDRAM memory on the Local Bus. 111 */ 112 void lbc_sdram_init(void) 113 { 114 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 115 116 uint idx; 117 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 118 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 119 uint lsdmr_common; 120 121 puts("LBC SDRAM: "); 122 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, 123 "\n"); 124 125 /* 126 * Setup SDRAM Base and Option Registers 127 */ 128 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 129 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 130 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 131 asm("msync"); 132 133 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 134 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 135 asm("msync"); 136 137 /* 138 * MPC8548 uses "new" 15-16 style addressing. 139 */ 140 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 141 lsdmr_common |= LSDMR_BSMA1516; 142 143 /* 144 * Issue PRECHARGE ALL command. 145 */ 146 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 147 asm("sync;msync"); 148 *sdram_addr = 0xff; 149 ppcDcbf((unsigned long) sdram_addr); 150 udelay(100); 151 152 /* 153 * Issue 8 AUTO REFRESH commands. 154 */ 155 for (idx = 0; idx < 8; idx++) { 156 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 157 asm("sync;msync"); 158 *sdram_addr = 0xff; 159 ppcDcbf((unsigned long) sdram_addr); 160 udelay(100); 161 } 162 163 /* 164 * Issue 8 MODE-set command. 165 */ 166 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 167 asm("sync;msync"); 168 *sdram_addr = 0xff; 169 ppcDcbf((unsigned long) sdram_addr); 170 udelay(100); 171 172 /* 173 * Issue NORMAL OP command. 174 */ 175 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 176 asm("sync;msync"); 177 *sdram_addr = 0xff; 178 ppcDcbf((unsigned long) sdram_addr); 179 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 180 181 #endif /* enable SDRAM init */ 182 } 183 184 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) 185 /* For some reason the Tundra PCI bridge shows up on itself as a 186 * different device. Work around that by refusing to configure it. 187 */ 188 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 189 190 static struct pci_config_table pci_mpc85xxcds_config_table[] = { 191 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 192 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 193 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 194 mpc85xx_config_via_usbide, {0,0,0}}, 195 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 196 mpc85xx_config_via_usb, {0,0,0}}, 197 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 198 mpc85xx_config_via_usb2, {0,0,0}}, 199 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 200 mpc85xx_config_via_power, {0,0,0}}, 201 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 202 mpc85xx_config_via_ac97, {0,0,0}}, 203 {}, 204 }; 205 206 static struct pci_controller pci1_hose; 207 #endif /* CONFIG_PCI */ 208 209 void pci_init_board(void) 210 { 211 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 212 struct fsl_pci_info pci_info; 213 u32 devdisr, pordevsr, io_sel; 214 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 215 int first_free_busno = 0; 216 char buf[32]; 217 218 devdisr = in_be32(&gur->devdisr); 219 pordevsr = in_be32(&gur->pordevsr); 220 porpllsr = in_be32(&gur->porpllsr); 221 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 222 223 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 224 225 #ifdef CONFIG_PCI1 226 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 227 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ 228 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 229 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 230 231 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 232 SET_STD_PCI_INFO(pci_info, 1); 233 set_next_law(pci_info.mem_phys, 234 law_size_bits(pci_info.mem_size), pci_info.law); 235 set_next_law(pci_info.io_phys, 236 law_size_bits(pci_info.io_size), pci_info.law); 237 238 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 239 printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 240 (pci_32) ? 32 : 64, 241 strmhz(buf, pci_speed), 242 pci_clk_sel ? "sync" : "async", 243 pci_agent ? "agent" : "host", 244 pci_arb ? "arbiter" : "external-arbiter", 245 pci_info.regs); 246 247 pci1_hose.config_table = pci_mpc85xxcds_config_table; 248 first_free_busno = fsl_pci_init_port(&pci_info, 249 &pci1_hose, first_free_busno); 250 251 #ifdef CONFIG_PCIX_CHECK 252 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) { 253 /* PCI-X init */ 254 if (CONFIG_SYS_CLK_FREQ < 66000000) 255 printf("PCI-X will only work at 66 MHz\n"); 256 257 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 258 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 259 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); 260 } 261 #endif 262 } else { 263 printf("PCI1: disabled\n"); 264 } 265 266 puts("\n"); 267 #else 268 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 269 #endif 270 271 #ifdef CONFIG_PCI2 272 { 273 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ 274 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 275 if (pci_dual) { 276 printf("PCI2: 32 bit, 66 MHz, %s\n", 277 pci2_clk_sel ? "sync" : "async"); 278 } else { 279 printf("PCI2: disabled\n"); 280 } 281 } 282 #else 283 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ 284 #endif /* CONFIG_PCI2 */ 285 286 fsl_pcie_init_board(first_free_busno); 287 } 288 289 void configure_rgmii(void) 290 { 291 unsigned short temp; 292 293 /* Change the resistors for the PHY */ 294 /* This is needed to get the RGMII working for the 1.3+ 295 * CDS cards */ 296 if (get_board_version() == 0x13) { 297 miiphy_write(DEFAULT_MII_NAME, 298 TSEC1_PHY_ADDR, 29, 18); 299 300 miiphy_read(DEFAULT_MII_NAME, 301 TSEC1_PHY_ADDR, 30, &temp); 302 303 temp = (temp & 0xf03f); 304 temp |= 2 << 9; /* 36 ohm */ 305 temp |= 2 << 6; /* 39 ohm */ 306 307 miiphy_write(DEFAULT_MII_NAME, 308 TSEC1_PHY_ADDR, 30, temp); 309 310 miiphy_write(DEFAULT_MII_NAME, 311 TSEC1_PHY_ADDR, 29, 3); 312 313 miiphy_write(DEFAULT_MII_NAME, 314 TSEC1_PHY_ADDR, 30, 0x8000); 315 } 316 317 return; 318 } 319 320 #ifdef CONFIG_TSEC_ENET 321 int board_eth_init(bd_t *bis) 322 { 323 struct fsl_pq_mdio_info mdio_info; 324 struct tsec_info_struct tsec_info[4]; 325 int num = 0; 326 327 #ifdef CONFIG_TSEC1 328 SET_STD_TSEC_INFO(tsec_info[num], 1); 329 num++; 330 #endif 331 #ifdef CONFIG_TSEC2 332 SET_STD_TSEC_INFO(tsec_info[num], 2); 333 num++; 334 #endif 335 #ifdef CONFIG_TSEC3 336 /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */ 337 if (get_board_version() >= 0x13) { 338 SET_STD_TSEC_INFO(tsec_info[num], 3); 339 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; 340 num++; 341 } 342 #endif 343 #ifdef CONFIG_TSEC4 344 /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */ 345 if (get_board_version() >= 0x13) { 346 SET_STD_TSEC_INFO(tsec_info[num], 4); 347 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; 348 num++; 349 } 350 #endif 351 352 if (!num) { 353 printf("No TSECs initialized\n"); 354 355 return 0; 356 } 357 358 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 359 mdio_info.name = DEFAULT_MII_NAME; 360 fsl_pq_mdio_init(bis, &mdio_info); 361 362 tsec_eth_init(bis, tsec_info, num); 363 configure_rgmii(); 364 365 return pci_eth_init(bis); 366 } 367 #endif 368 369 #if defined(CONFIG_OF_BOARD_SETUP) 370 void ft_pci_setup(void *blob, bd_t *bd) 371 { 372 FT_FSL_PCI_SETUP; 373 } 374 #endif 375