1 /* 2 * Copyright 2004, 2007 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/immap_fsl_pci.h> 30 #include <spd.h> 31 #include <miiphy.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 35 #include "../common/cadmus.h" 36 #include "../common/eeprom.h" 37 #include "../common/via.h" 38 39 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 40 extern void ddr_enable_ecc(unsigned int dram_size); 41 #endif 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 extern long int spd_sdram(void); 46 47 void local_bus_init(void); 48 void sdram_init(void); 49 50 int board_early_init_f (void) 51 { 52 return 0; 53 } 54 55 int checkboard (void) 56 { 57 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 58 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); 59 60 /* PCI slot in USER bits CSR[6:7] by convention. */ 61 uint pci_slot = get_pci_slot (); 62 63 uint cpu_board_rev = get_cpu_board_revision (); 64 65 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", 66 get_board_version (), pci_slot); 67 68 printf ("CPU Board Revision %d.%d (0x%04x)\n", 69 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), 70 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); 71 /* 72 * Initialize local bus. 73 */ 74 local_bus_init (); 75 76 /* 77 * Fix CPU2 errata: A core hang possible while executing a 78 * msync instruction and a snoopable transaction from an I/O 79 * master tagged to make quick forward progress is present. 80 */ 81 ecm->eebpcr |= (1 << 16); 82 83 /* 84 * Hack TSEC 3 and 4 IO voltages. 85 */ 86 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ 87 88 ecm->eedr = 0xffffffff; /* clear ecm errors */ 89 ecm->eeer = 0xffffffff; /* enable ecm errors */ 90 return 0; 91 } 92 93 long int 94 initdram(int board_type) 95 { 96 long dram_size = 0; 97 98 puts("Initializing\n"); 99 100 #if defined(CONFIG_DDR_DLL) 101 { 102 /* 103 * Work around to stabilize DDR DLL MSYNC_IN. 104 * Errata DDR9 seems to have been fixed. 105 * This is now the workaround for Errata DDR11: 106 * Override DLL = 1, Course Adj = 1, Tap Select = 0 107 */ 108 109 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 110 111 gur->ddrdllcr = 0x81000000; 112 asm("sync;isync;msync"); 113 udelay(200); 114 } 115 #endif 116 dram_size = spd_sdram(); 117 118 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 119 /* 120 * Initialize and enable DDR ECC. 121 */ 122 ddr_enable_ecc(dram_size); 123 #endif 124 /* 125 * SDRAM Initialization 126 */ 127 sdram_init(); 128 129 puts(" DDR: "); 130 return dram_size; 131 } 132 133 /* 134 * Initialize Local Bus 135 */ 136 void 137 local_bus_init(void) 138 { 139 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 140 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 141 142 uint clkdiv; 143 uint lbc_hz; 144 sys_info_t sysinfo; 145 146 get_sys_info(&sysinfo); 147 clkdiv = (lbc->lcrr & 0x0f) * 2; 148 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 149 150 gur->lbiuiplldcr1 = 0x00078080; 151 if (clkdiv == 16) { 152 gur->lbiuiplldcr0 = 0x7c0f1bf0; 153 } else if (clkdiv == 8) { 154 gur->lbiuiplldcr0 = 0x6c0f1bf0; 155 } else if (clkdiv == 4) { 156 gur->lbiuiplldcr0 = 0x5c0f1bf0; 157 } 158 159 lbc->lcrr |= 0x00030000; 160 161 asm("sync;isync;msync"); 162 163 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 164 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 165 } 166 167 /* 168 * Initialize SDRAM memory on the Local Bus. 169 */ 170 void 171 sdram_init(void) 172 { 173 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) 174 175 uint idx; 176 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 177 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 178 uint cpu_board_rev; 179 uint lsdmr_common; 180 181 puts(" SDRAM: "); 182 183 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 184 185 /* 186 * Setup SDRAM Base and Option Registers 187 */ 188 lbc->or2 = CFG_OR2_PRELIM; 189 asm("msync"); 190 191 lbc->br2 = CFG_BR2_PRELIM; 192 asm("msync"); 193 194 lbc->lbcr = CFG_LBC_LBCR; 195 asm("msync"); 196 197 198 lbc->lsrt = CFG_LBC_LSRT; 199 lbc->mrtpr = CFG_LBC_MRTPR; 200 asm("msync"); 201 202 /* 203 * MPC8548 uses "new" 15-16 style addressing. 204 */ 205 cpu_board_rev = get_cpu_board_revision(); 206 lsdmr_common = CFG_LBC_LSDMR_COMMON; 207 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; 208 209 /* 210 * Issue PRECHARGE ALL command. 211 */ 212 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; 213 asm("sync;msync"); 214 *sdram_addr = 0xff; 215 ppcDcbf((unsigned long) sdram_addr); 216 udelay(100); 217 218 /* 219 * Issue 8 AUTO REFRESH commands. 220 */ 221 for (idx = 0; idx < 8; idx++) { 222 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; 223 asm("sync;msync"); 224 *sdram_addr = 0xff; 225 ppcDcbf((unsigned long) sdram_addr); 226 udelay(100); 227 } 228 229 /* 230 * Issue 8 MODE-set command. 231 */ 232 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; 233 asm("sync;msync"); 234 *sdram_addr = 0xff; 235 ppcDcbf((unsigned long) sdram_addr); 236 udelay(100); 237 238 /* 239 * Issue NORMAL OP command. 240 */ 241 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; 242 asm("sync;msync"); 243 *sdram_addr = 0xff; 244 ppcDcbf((unsigned long) sdram_addr); 245 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 246 247 #endif /* enable SDRAM init */ 248 } 249 250 #if defined(CFG_DRAM_TEST) 251 int 252 testdram(void) 253 { 254 uint *pstart = (uint *) CFG_MEMTEST_START; 255 uint *pend = (uint *) CFG_MEMTEST_END; 256 uint *p; 257 258 printf("Testing DRAM from 0x%08x to 0x%08x\n", 259 CFG_MEMTEST_START, 260 CFG_MEMTEST_END); 261 262 printf("DRAM test phase 1:\n"); 263 for (p = pstart; p < pend; p++) 264 *p = 0xaaaaaaaa; 265 266 for (p = pstart; p < pend; p++) { 267 if (*p != 0xaaaaaaaa) { 268 printf ("DRAM test fails at: %08x\n", (uint) p); 269 return 1; 270 } 271 } 272 273 printf("DRAM test phase 2:\n"); 274 for (p = pstart; p < pend; p++) 275 *p = 0x55555555; 276 277 for (p = pstart; p < pend; p++) { 278 if (*p != 0x55555555) { 279 printf ("DRAM test fails at: %08x\n", (uint) p); 280 return 1; 281 } 282 } 283 284 printf("DRAM test passed.\n"); 285 return 0; 286 } 287 #endif 288 289 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) 290 /* For some reason the Tundra PCI bridge shows up on itself as a 291 * different device. Work around that by refusing to configure it. 292 */ 293 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 294 295 static struct pci_config_table pci_mpc85xxcds_config_table[] = { 296 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 297 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 298 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 299 mpc85xx_config_via_usbide, {0,0,0}}, 300 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 301 mpc85xx_config_via_usb, {0,0,0}}, 302 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 303 mpc85xx_config_via_usb2, {0,0,0}}, 304 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 305 mpc85xx_config_via_power, {0,0,0}}, 306 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 307 mpc85xx_config_via_ac97, {0,0,0}}, 308 {}, 309 }; 310 311 static struct pci_controller pci1_hose = { 312 config_table: pci_mpc85xxcds_config_table}; 313 #endif /* CONFIG_PCI */ 314 315 #ifdef CONFIG_PCI2 316 static struct pci_controller pci2_hose; 317 #endif /* CONFIG_PCI2 */ 318 319 #ifdef CONFIG_PCIE1 320 static struct pci_controller pcie1_hose; 321 #endif /* CONFIG_PCIE1 */ 322 323 int first_free_busno=0; 324 325 void 326 pci_init_board(void) 327 { 328 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 329 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 330 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 331 332 333 #ifdef CONFIG_PCI1 334 { 335 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 336 extern void fsl_pci_init(struct pci_controller *hose); 337 struct pci_controller *hose = &pci1_hose; 338 struct pci_config_table *table; 339 340 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ 341 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 342 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 343 344 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); 345 346 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 347 348 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 349 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", 350 (pci_32) ? 32 : 64, 351 (pci_speed == 33333000) ? "33" : 352 (pci_speed == 66666000) ? "66" : "unknown", 353 pci_clk_sel ? "sync" : "async", 354 pci_agent ? "agent" : "host", 355 pci_arb ? "arbiter" : "external-arbiter" 356 ); 357 358 359 /* inbound */ 360 pci_set_region(hose->regions + 0, 361 CFG_PCI_MEMORY_BUS, 362 CFG_PCI_MEMORY_PHYS, 363 CFG_PCI_MEMORY_SIZE, 364 PCI_REGION_MEM | PCI_REGION_MEMORY); 365 366 367 /* outbound memory */ 368 pci_set_region(hose->regions + 1, 369 CFG_PCI1_MEM_BASE, 370 CFG_PCI1_MEM_PHYS, 371 CFG_PCI1_MEM_SIZE, 372 PCI_REGION_MEM); 373 374 /* outbound io */ 375 pci_set_region(hose->regions + 2, 376 CFG_PCI1_IO_BASE, 377 CFG_PCI1_IO_PHYS, 378 CFG_PCI1_IO_SIZE, 379 PCI_REGION_IO); 380 hose->region_count = 3; 381 382 /* relocate config table pointers */ 383 hose->config_table = \ 384 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); 385 for (table = hose->config_table; table && table->vendor; table++) 386 table->config_device += gd->reloc_off; 387 388 hose->first_busno=first_free_busno; 389 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 390 391 fsl_pci_init(hose); 392 first_free_busno=hose->last_busno+1; 393 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 394 #ifdef CONFIG_PCIX_CHECK 395 if (!(gur->pordevsr & PORDEVSR_PCI)) { 396 /* PCI-X init */ 397 if (CONFIG_SYS_CLK_FREQ < 66000000) 398 printf("PCI-X will only work at 66 MHz\n"); 399 400 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 401 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 402 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); 403 } 404 #endif 405 } else { 406 printf (" PCI: disabled\n"); 407 } 408 } 409 #else 410 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 411 #endif 412 413 #ifdef CONFIG_PCI2 414 { 415 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ 416 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 417 if (pci_dual) { 418 printf (" PCI2: 32 bit, 66 MHz, %s\n", 419 pci2_clk_sel ? "sync" : "async"); 420 } else { 421 printf (" PCI2: disabled\n"); 422 } 423 } 424 #else 425 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ 426 #endif /* CONFIG_PCI2 */ 427 428 #ifdef CONFIG_PCIE1 429 { 430 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 431 extern void fsl_pci_init(struct pci_controller *hose); 432 struct pci_controller *hose = &pcie1_hose; 433 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 434 435 int pcie_configured = io_sel >= 1; 436 437 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 438 printf ("\n PCIE connected to slot as %s (base address %x)", 439 pcie_ep ? "End Point" : "Root Complex", 440 (uint)pci); 441 442 if (pci->pme_msg_det) { 443 pci->pme_msg_det = 0xffffffff; 444 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 445 } 446 printf ("\n"); 447 448 /* inbound */ 449 pci_set_region(hose->regions + 0, 450 CFG_PCI_MEMORY_BUS, 451 CFG_PCI_MEMORY_PHYS, 452 CFG_PCI_MEMORY_SIZE, 453 PCI_REGION_MEM | PCI_REGION_MEMORY); 454 455 /* outbound memory */ 456 pci_set_region(hose->regions + 1, 457 CFG_PCIE1_MEM_BASE, 458 CFG_PCIE1_MEM_PHYS, 459 CFG_PCIE1_MEM_SIZE, 460 PCI_REGION_MEM); 461 462 /* outbound io */ 463 pci_set_region(hose->regions + 2, 464 CFG_PCIE1_IO_BASE, 465 CFG_PCIE1_IO_PHYS, 466 CFG_PCIE1_IO_SIZE, 467 PCI_REGION_IO); 468 469 hose->region_count = 3; 470 471 hose->first_busno=first_free_busno; 472 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 473 474 fsl_pci_init(hose); 475 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); 476 477 first_free_busno=hose->last_busno+1; 478 479 } else { 480 printf (" PCIE: disabled\n"); 481 } 482 } 483 #else 484 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 485 #endif 486 487 } 488 489 int last_stage_init(void) 490 { 491 unsigned short temp; 492 493 /* Change the resistors for the PHY */ 494 /* This is needed to get the RGMII working for the 1.3+ 495 * CDS cards */ 496 if (get_board_version() == 0x13) { 497 miiphy_write(CONFIG_TSEC1_NAME, 498 TSEC1_PHY_ADDR, 29, 18); 499 500 miiphy_read(CONFIG_TSEC1_NAME, 501 TSEC1_PHY_ADDR, 30, &temp); 502 503 temp = (temp & 0xf03f); 504 temp |= 2 << 9; /* 36 ohm */ 505 temp |= 2 << 6; /* 39 ohm */ 506 507 miiphy_write(CONFIG_TSEC1_NAME, 508 TSEC1_PHY_ADDR, 30, temp); 509 510 miiphy_write(CONFIG_TSEC1_NAME, 511 TSEC1_PHY_ADDR, 29, 3); 512 513 miiphy_write(CONFIG_TSEC1_NAME, 514 TSEC1_PHY_ADDR, 30, 0x8000); 515 } 516 517 return 0; 518 } 519 520 521 #if defined(CONFIG_OF_BOARD_SETUP) 522 void 523 ft_pci_setup(void *blob, bd_t *bd) 524 { 525 int node, tmp[2]; 526 const char *path; 527 528 node = fdt_path_offset(blob, "/aliases"); 529 tmp[0] = 0; 530 if (node >= 0) { 531 #ifdef CONFIG_PCI1 532 path = fdt_getprop(blob, node, "pci0", NULL); 533 if (path) { 534 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 535 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 536 } 537 #endif 538 #ifdef CONFIG_PCIE1 539 path = fdt_getprop(blob, node, "pci1", NULL); 540 if (path) { 541 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 542 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 543 } 544 #endif 545 } 546 } 547 #endif 548