1 /*
2  * Copyright 2004, 2007 Freescale Semiconductor.
3  *
4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #include <common.h>
26 #include <pci.h>
27 #include <asm/processor.h>
28 #include <asm/mmu.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <spd_sdram.h>
33 #include <miiphy.h>
34 #include <libfdt.h>
35 #include <fdt_support.h>
36 
37 #include "../common/cadmus.h"
38 #include "../common/eeprom.h"
39 #include "../common/via.h"
40 
41 DECLARE_GLOBAL_DATA_PTR;
42 
43 void local_bus_init(void);
44 void sdram_init(void);
45 
46 int checkboard (void)
47 {
48 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
50 
51 	/* PCI slot in USER bits CSR[6:7] by convention. */
52 	uint pci_slot = get_pci_slot ();
53 
54 	uint cpu_board_rev = get_cpu_board_revision ();
55 
56 	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
57 		get_board_version (), pci_slot);
58 
59 	printf ("CPU Board Revision %d.%d (0x%04x)\n",
60 		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
61 		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
62 	/*
63 	 * Initialize local bus.
64 	 */
65 	local_bus_init ();
66 
67 	/*
68 	 * Hack TSEC 3 and 4 IO voltages.
69 	 */
70 	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */
71 
72 	ecm->eedr = 0xffffffff;		/* clear ecm errors */
73 	ecm->eeer = 0xffffffff;		/* enable ecm errors */
74 	return 0;
75 }
76 
77 phys_size_t
78 initdram(int board_type)
79 {
80 	long dram_size = 0;
81 
82 	puts("Initializing\n");
83 
84 #if defined(CONFIG_DDR_DLL)
85 	{
86 		/*
87 		 * Work around to stabilize DDR DLL MSYNC_IN.
88 		 * Errata DDR9 seems to have been fixed.
89 		 * This is now the workaround for Errata DDR11:
90 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
91 		 */
92 
93 		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
94 
95 		gur->ddrdllcr = 0x81000000;
96 		asm("sync;isync;msync");
97 		udelay(200);
98 	}
99 #endif
100 
101 	dram_size = fsl_ddr_sdram();
102 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
103 	dram_size *= 0x100000;
104 
105 	/*
106 	 * SDRAM Initialization
107 	 */
108 	sdram_init();
109 
110 	puts("    DDR: ");
111 	return dram_size;
112 }
113 
114 /*
115  * Initialize Local Bus
116  */
117 void
118 local_bus_init(void)
119 {
120 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
121 	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
122 
123 	uint clkdiv;
124 	uint lbc_hz;
125 	sys_info_t sysinfo;
126 
127 	get_sys_info(&sysinfo);
128 	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
129 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
130 
131 	gur->lbiuiplldcr1 = 0x00078080;
132 	if (clkdiv == 16) {
133 		gur->lbiuiplldcr0 = 0x7c0f1bf0;
134 	} else if (clkdiv == 8) {
135 		gur->lbiuiplldcr0 = 0x6c0f1bf0;
136 	} else if (clkdiv == 4) {
137 		gur->lbiuiplldcr0 = 0x5c0f1bf0;
138 	}
139 
140 	lbc->lcrr |= 0x00030000;
141 
142 	asm("sync;isync;msync");
143 
144 	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
145 	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
146 }
147 
148 /*
149  * Initialize SDRAM memory on the Local Bus.
150  */
151 void
152 sdram_init(void)
153 {
154 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
155 
156 	uint idx;
157 	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
158 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
159 	uint cpu_board_rev;
160 	uint lsdmr_common;
161 
162 	puts("    SDRAM: ");
163 
164 	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
165 
166 	/*
167 	 * Setup SDRAM Base and Option Registers
168 	 */
169 	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
170 	asm("msync");
171 
172 	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
173 	asm("msync");
174 
175 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
176 	asm("msync");
177 
178 
179 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
180 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
181 	asm("msync");
182 
183 	/*
184 	 * MPC8548 uses "new" 15-16 style addressing.
185 	 */
186 	cpu_board_rev = get_cpu_board_revision();
187 	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
188 	lsdmr_common |= LSDMR_BSMA1516;
189 
190 	/*
191 	 * Issue PRECHARGE ALL command.
192 	 */
193 	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
194 	asm("sync;msync");
195 	*sdram_addr = 0xff;
196 	ppcDcbf((unsigned long) sdram_addr);
197 	udelay(100);
198 
199 	/*
200 	 * Issue 8 AUTO REFRESH commands.
201 	 */
202 	for (idx = 0; idx < 8; idx++) {
203 		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
204 		asm("sync;msync");
205 		*sdram_addr = 0xff;
206 		ppcDcbf((unsigned long) sdram_addr);
207 		udelay(100);
208 	}
209 
210 	/*
211 	 * Issue 8 MODE-set command.
212 	 */
213 	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
214 	asm("sync;msync");
215 	*sdram_addr = 0xff;
216 	ppcDcbf((unsigned long) sdram_addr);
217 	udelay(100);
218 
219 	/*
220 	 * Issue NORMAL OP command.
221 	 */
222 	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
223 	asm("sync;msync");
224 	*sdram_addr = 0xff;
225 	ppcDcbf((unsigned long) sdram_addr);
226 	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
227 
228 #endif	/* enable SDRAM init */
229 }
230 
231 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
232 /* For some reason the Tundra PCI bridge shows up on itself as a
233  * different device.  Work around that by refusing to configure it.
234  */
235 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
236 
237 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
238 	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
239 	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
240 	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
241 		mpc85xx_config_via_usbide, {0,0,0}},
242 	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
243 		mpc85xx_config_via_usb, {0,0,0}},
244 	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
245 		mpc85xx_config_via_usb2, {0,0,0}},
246 	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
247 		mpc85xx_config_via_power, {0,0,0}},
248 	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
249 		mpc85xx_config_via_ac97, {0,0,0}},
250 	{},
251 };
252 
253 static struct pci_controller pci1_hose = {
254 	config_table: pci_mpc85xxcds_config_table};
255 #endif	/* CONFIG_PCI */
256 
257 #ifdef CONFIG_PCI2
258 static struct pci_controller pci2_hose;
259 #endif	/* CONFIG_PCI2 */
260 
261 #ifdef CONFIG_PCIE1
262 static struct pci_controller pcie1_hose;
263 #endif	/* CONFIG_PCIE1 */
264 
265 int first_free_busno=0;
266 
267 void
268 pci_init_board(void)
269 {
270 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
271 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
272 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
273 
274 
275 #ifdef CONFIG_PCI1
276 {
277 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
278 	struct pci_controller *hose = &pci1_hose;
279 	struct pci_region *r = hose->regions;
280 
281 	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
282 	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
283 	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */
284 
285 	uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
286 
287 	uint pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
288 
289 	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
290 		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
291 			(pci_32) ? 32 : 64,
292 			(pci_speed == 33333000) ? "33" :
293 			(pci_speed == 66666000) ? "66" : "unknown",
294 			pci_clk_sel ? "sync" : "async",
295 			pci_agent ? "agent" : "host",
296 			pci_arb ? "arbiter" : "external-arbiter"
297 			);
298 
299 		/* outbound memory */
300 		pci_set_region(r++,
301 			       CONFIG_SYS_PCI1_MEM_BUS,
302 			       CONFIG_SYS_PCI1_MEM_PHYS,
303 			       CONFIG_SYS_PCI1_MEM_SIZE,
304 			       PCI_REGION_MEM);
305 
306 		/* outbound io */
307 		pci_set_region(r++,
308 			       CONFIG_SYS_PCI1_IO_BUS,
309 			       CONFIG_SYS_PCI1_IO_PHYS,
310 			       CONFIG_SYS_PCI1_IO_SIZE,
311 			       PCI_REGION_IO);
312 		hose->region_count = r - hose->regions;
313 
314 		hose->first_busno=first_free_busno;
315 
316 		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
317 		first_free_busno=hose->last_busno+1;
318 		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
319 #ifdef CONFIG_PCIX_CHECK
320 		if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
321 			/* PCI-X init */
322 			if (CONFIG_SYS_CLK_FREQ < 66000000)
323 				printf("PCI-X will only work at 66 MHz\n");
324 
325 			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
326 				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
327 			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
328 		}
329 #endif
330 	} else {
331 		printf ("    PCI: disabled\n");
332 	}
333 }
334 #else
335 	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
336 #endif
337 
338 #ifdef CONFIG_PCI2
339 {
340 	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
341 	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
342 	if (pci_dual) {
343 		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
344 			pci2_clk_sel ? "sync" : "async");
345 	} else {
346 		printf ("    PCI2: disabled\n");
347 	}
348 }
349 #else
350 	gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
351 #endif /* CONFIG_PCI2 */
352 
353 #ifdef CONFIG_PCIE1
354 {
355 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
356 	struct pci_controller *hose = &pcie1_hose;
357 	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
358 	struct pci_region *r = hose->regions;
359 
360 	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
361 
362 	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
363 		printf ("\n    PCIE connected to slot as %s (base address %x)",
364 			pcie_ep ? "End Point" : "Root Complex",
365 			(uint)pci);
366 
367 		if (pci->pme_msg_det) {
368 			pci->pme_msg_det = 0xffffffff;
369 			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
370 		}
371 		printf ("\n");
372 
373 		/* outbound memory */
374 		pci_set_region(r++,
375 			       CONFIG_SYS_PCIE1_MEM_BUS,
376 			       CONFIG_SYS_PCIE1_MEM_PHYS,
377 			       CONFIG_SYS_PCIE1_MEM_SIZE,
378 			       PCI_REGION_MEM);
379 
380 		/* outbound io */
381 		pci_set_region(r++,
382 			       CONFIG_SYS_PCIE1_IO_BUS,
383 			       CONFIG_SYS_PCIE1_IO_PHYS,
384 			       CONFIG_SYS_PCIE1_IO_SIZE,
385 			       PCI_REGION_IO);
386 
387 		hose->region_count = r - hose->regions;
388 
389 		hose->first_busno=first_free_busno;
390 
391 		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
392 		printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
393 
394 		first_free_busno=hose->last_busno+1;
395 
396 	} else {
397 		printf ("    PCIE: disabled\n");
398 	}
399  }
400 #else
401 	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
402 #endif
403 
404 }
405 
406 int last_stage_init(void)
407 {
408 	unsigned short temp;
409 
410 	/* Change the resistors for the PHY */
411 	/* This is needed to get the RGMII working for the 1.3+
412 	 * CDS cards */
413 	if (get_board_version() ==  0x13) {
414 		miiphy_write(CONFIG_TSEC1_NAME,
415 				TSEC1_PHY_ADDR, 29, 18);
416 
417 		miiphy_read(CONFIG_TSEC1_NAME,
418 				TSEC1_PHY_ADDR, 30, &temp);
419 
420 		temp = (temp & 0xf03f);
421 		temp |= 2 << 9;		/* 36 ohm */
422 		temp |= 2 << 6;		/* 39 ohm */
423 
424 		miiphy_write(CONFIG_TSEC1_NAME,
425 				TSEC1_PHY_ADDR, 30, temp);
426 
427 		miiphy_write(CONFIG_TSEC1_NAME,
428 				TSEC1_PHY_ADDR, 29, 3);
429 
430 		miiphy_write(CONFIG_TSEC1_NAME,
431 				TSEC1_PHY_ADDR, 30, 0x8000);
432 	}
433 
434 	return 0;
435 }
436 
437 
438 #if defined(CONFIG_OF_BOARD_SETUP)
439 void ft_pci_setup(void *blob, bd_t *bd)
440 {
441 #ifdef CONFIG_PCI1
442 	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
443 #endif
444 #ifdef CONFIG_PCIE1
445 	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
446 #endif
447 }
448 #endif
449