1 /* 2 * Copyright 2004, 2007 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/immap_fsl_pci.h> 30 #include <spd_sdram.h> 31 #include <miiphy.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 35 #include "../common/cadmus.h" 36 #include "../common/eeprom.h" 37 #include "../common/via.h" 38 39 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 40 extern void ddr_enable_ecc(unsigned int dram_size); 41 #endif 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 void local_bus_init(void); 46 void sdram_init(void); 47 48 int board_early_init_f (void) 49 { 50 return 0; 51 } 52 53 int checkboard (void) 54 { 55 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 56 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); 57 58 /* PCI slot in USER bits CSR[6:7] by convention. */ 59 uint pci_slot = get_pci_slot (); 60 61 uint cpu_board_rev = get_cpu_board_revision (); 62 63 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", 64 get_board_version (), pci_slot); 65 66 printf ("CPU Board Revision %d.%d (0x%04x)\n", 67 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), 68 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); 69 /* 70 * Initialize local bus. 71 */ 72 local_bus_init (); 73 74 /* 75 * Fix CPU2 errata: A core hang possible while executing a 76 * msync instruction and a snoopable transaction from an I/O 77 * master tagged to make quick forward progress is present. 78 */ 79 ecm->eebpcr |= (1 << 16); 80 81 /* 82 * Hack TSEC 3 and 4 IO voltages. 83 */ 84 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ 85 86 ecm->eedr = 0xffffffff; /* clear ecm errors */ 87 ecm->eeer = 0xffffffff; /* enable ecm errors */ 88 return 0; 89 } 90 91 long int 92 initdram(int board_type) 93 { 94 long dram_size = 0; 95 96 puts("Initializing\n"); 97 98 #if defined(CONFIG_DDR_DLL) 99 { 100 /* 101 * Work around to stabilize DDR DLL MSYNC_IN. 102 * Errata DDR9 seems to have been fixed. 103 * This is now the workaround for Errata DDR11: 104 * Override DLL = 1, Course Adj = 1, Tap Select = 0 105 */ 106 107 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 108 109 gur->ddrdllcr = 0x81000000; 110 asm("sync;isync;msync"); 111 udelay(200); 112 } 113 #endif 114 dram_size = spd_sdram(); 115 116 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 117 /* 118 * Initialize and enable DDR ECC. 119 */ 120 ddr_enable_ecc(dram_size); 121 #endif 122 /* 123 * SDRAM Initialization 124 */ 125 sdram_init(); 126 127 puts(" DDR: "); 128 return dram_size; 129 } 130 131 /* 132 * Initialize Local Bus 133 */ 134 void 135 local_bus_init(void) 136 { 137 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 138 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 139 140 uint clkdiv; 141 uint lbc_hz; 142 sys_info_t sysinfo; 143 144 get_sys_info(&sysinfo); 145 clkdiv = (lbc->lcrr & 0x0f) * 2; 146 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 147 148 gur->lbiuiplldcr1 = 0x00078080; 149 if (clkdiv == 16) { 150 gur->lbiuiplldcr0 = 0x7c0f1bf0; 151 } else if (clkdiv == 8) { 152 gur->lbiuiplldcr0 = 0x6c0f1bf0; 153 } else if (clkdiv == 4) { 154 gur->lbiuiplldcr0 = 0x5c0f1bf0; 155 } 156 157 lbc->lcrr |= 0x00030000; 158 159 asm("sync;isync;msync"); 160 161 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 162 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 163 } 164 165 /* 166 * Initialize SDRAM memory on the Local Bus. 167 */ 168 void 169 sdram_init(void) 170 { 171 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) 172 173 uint idx; 174 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 175 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 176 uint cpu_board_rev; 177 uint lsdmr_common; 178 179 puts(" SDRAM: "); 180 181 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 182 183 /* 184 * Setup SDRAM Base and Option Registers 185 */ 186 lbc->or2 = CFG_OR2_PRELIM; 187 asm("msync"); 188 189 lbc->br2 = CFG_BR2_PRELIM; 190 asm("msync"); 191 192 lbc->lbcr = CFG_LBC_LBCR; 193 asm("msync"); 194 195 196 lbc->lsrt = CFG_LBC_LSRT; 197 lbc->mrtpr = CFG_LBC_MRTPR; 198 asm("msync"); 199 200 /* 201 * MPC8548 uses "new" 15-16 style addressing. 202 */ 203 cpu_board_rev = get_cpu_board_revision(); 204 lsdmr_common = CFG_LBC_LSDMR_COMMON; 205 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; 206 207 /* 208 * Issue PRECHARGE ALL command. 209 */ 210 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; 211 asm("sync;msync"); 212 *sdram_addr = 0xff; 213 ppcDcbf((unsigned long) sdram_addr); 214 udelay(100); 215 216 /* 217 * Issue 8 AUTO REFRESH commands. 218 */ 219 for (idx = 0; idx < 8; idx++) { 220 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; 221 asm("sync;msync"); 222 *sdram_addr = 0xff; 223 ppcDcbf((unsigned long) sdram_addr); 224 udelay(100); 225 } 226 227 /* 228 * Issue 8 MODE-set command. 229 */ 230 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; 231 asm("sync;msync"); 232 *sdram_addr = 0xff; 233 ppcDcbf((unsigned long) sdram_addr); 234 udelay(100); 235 236 /* 237 * Issue NORMAL OP command. 238 */ 239 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; 240 asm("sync;msync"); 241 *sdram_addr = 0xff; 242 ppcDcbf((unsigned long) sdram_addr); 243 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 244 245 #endif /* enable SDRAM init */ 246 } 247 248 #if defined(CFG_DRAM_TEST) 249 int 250 testdram(void) 251 { 252 uint *pstart = (uint *) CFG_MEMTEST_START; 253 uint *pend = (uint *) CFG_MEMTEST_END; 254 uint *p; 255 256 printf("Testing DRAM from 0x%08x to 0x%08x\n", 257 CFG_MEMTEST_START, 258 CFG_MEMTEST_END); 259 260 printf("DRAM test phase 1:\n"); 261 for (p = pstart; p < pend; p++) 262 *p = 0xaaaaaaaa; 263 264 for (p = pstart; p < pend; p++) { 265 if (*p != 0xaaaaaaaa) { 266 printf ("DRAM test fails at: %08x\n", (uint) p); 267 return 1; 268 } 269 } 270 271 printf("DRAM test phase 2:\n"); 272 for (p = pstart; p < pend; p++) 273 *p = 0x55555555; 274 275 for (p = pstart; p < pend; p++) { 276 if (*p != 0x55555555) { 277 printf ("DRAM test fails at: %08x\n", (uint) p); 278 return 1; 279 } 280 } 281 282 printf("DRAM test passed.\n"); 283 return 0; 284 } 285 #endif 286 287 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) 288 /* For some reason the Tundra PCI bridge shows up on itself as a 289 * different device. Work around that by refusing to configure it. 290 */ 291 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 292 293 static struct pci_config_table pci_mpc85xxcds_config_table[] = { 294 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 295 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 296 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 297 mpc85xx_config_via_usbide, {0,0,0}}, 298 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 299 mpc85xx_config_via_usb, {0,0,0}}, 300 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 301 mpc85xx_config_via_usb2, {0,0,0}}, 302 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 303 mpc85xx_config_via_power, {0,0,0}}, 304 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 305 mpc85xx_config_via_ac97, {0,0,0}}, 306 {}, 307 }; 308 309 static struct pci_controller pci1_hose = { 310 config_table: pci_mpc85xxcds_config_table}; 311 #endif /* CONFIG_PCI */ 312 313 #ifdef CONFIG_PCI2 314 static struct pci_controller pci2_hose; 315 #endif /* CONFIG_PCI2 */ 316 317 #ifdef CONFIG_PCIE1 318 static struct pci_controller pcie1_hose; 319 #endif /* CONFIG_PCIE1 */ 320 321 int first_free_busno=0; 322 323 void 324 pci_init_board(void) 325 { 326 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 327 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 328 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 329 330 331 #ifdef CONFIG_PCI1 332 { 333 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 334 extern void fsl_pci_init(struct pci_controller *hose); 335 struct pci_controller *hose = &pci1_hose; 336 struct pci_config_table *table; 337 338 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ 339 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 340 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 341 342 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); 343 344 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 345 346 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 347 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", 348 (pci_32) ? 32 : 64, 349 (pci_speed == 33333000) ? "33" : 350 (pci_speed == 66666000) ? "66" : "unknown", 351 pci_clk_sel ? "sync" : "async", 352 pci_agent ? "agent" : "host", 353 pci_arb ? "arbiter" : "external-arbiter" 354 ); 355 356 357 /* inbound */ 358 pci_set_region(hose->regions + 0, 359 CFG_PCI_MEMORY_BUS, 360 CFG_PCI_MEMORY_PHYS, 361 CFG_PCI_MEMORY_SIZE, 362 PCI_REGION_MEM | PCI_REGION_MEMORY); 363 364 365 /* outbound memory */ 366 pci_set_region(hose->regions + 1, 367 CFG_PCI1_MEM_BASE, 368 CFG_PCI1_MEM_PHYS, 369 CFG_PCI1_MEM_SIZE, 370 PCI_REGION_MEM); 371 372 /* outbound io */ 373 pci_set_region(hose->regions + 2, 374 CFG_PCI1_IO_BASE, 375 CFG_PCI1_IO_PHYS, 376 CFG_PCI1_IO_SIZE, 377 PCI_REGION_IO); 378 hose->region_count = 3; 379 380 /* relocate config table pointers */ 381 hose->config_table = \ 382 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); 383 for (table = hose->config_table; table && table->vendor; table++) 384 table->config_device += gd->reloc_off; 385 386 hose->first_busno=first_free_busno; 387 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 388 389 fsl_pci_init(hose); 390 first_free_busno=hose->last_busno+1; 391 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 392 #ifdef CONFIG_PCIX_CHECK 393 if (!(gur->pordevsr & PORDEVSR_PCI)) { 394 /* PCI-X init */ 395 if (CONFIG_SYS_CLK_FREQ < 66000000) 396 printf("PCI-X will only work at 66 MHz\n"); 397 398 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 399 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 400 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); 401 } 402 #endif 403 } else { 404 printf (" PCI: disabled\n"); 405 } 406 } 407 #else 408 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 409 #endif 410 411 #ifdef CONFIG_PCI2 412 { 413 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ 414 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 415 if (pci_dual) { 416 printf (" PCI2: 32 bit, 66 MHz, %s\n", 417 pci2_clk_sel ? "sync" : "async"); 418 } else { 419 printf (" PCI2: disabled\n"); 420 } 421 } 422 #else 423 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ 424 #endif /* CONFIG_PCI2 */ 425 426 #ifdef CONFIG_PCIE1 427 { 428 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 429 extern void fsl_pci_init(struct pci_controller *hose); 430 struct pci_controller *hose = &pcie1_hose; 431 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 432 433 int pcie_configured = io_sel >= 1; 434 435 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 436 printf ("\n PCIE connected to slot as %s (base address %x)", 437 pcie_ep ? "End Point" : "Root Complex", 438 (uint)pci); 439 440 if (pci->pme_msg_det) { 441 pci->pme_msg_det = 0xffffffff; 442 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 443 } 444 printf ("\n"); 445 446 /* inbound */ 447 pci_set_region(hose->regions + 0, 448 CFG_PCI_MEMORY_BUS, 449 CFG_PCI_MEMORY_PHYS, 450 CFG_PCI_MEMORY_SIZE, 451 PCI_REGION_MEM | PCI_REGION_MEMORY); 452 453 /* outbound memory */ 454 pci_set_region(hose->regions + 1, 455 CFG_PCIE1_MEM_BASE, 456 CFG_PCIE1_MEM_PHYS, 457 CFG_PCIE1_MEM_SIZE, 458 PCI_REGION_MEM); 459 460 /* outbound io */ 461 pci_set_region(hose->regions + 2, 462 CFG_PCIE1_IO_BASE, 463 CFG_PCIE1_IO_PHYS, 464 CFG_PCIE1_IO_SIZE, 465 PCI_REGION_IO); 466 467 hose->region_count = 3; 468 469 hose->first_busno=first_free_busno; 470 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 471 472 fsl_pci_init(hose); 473 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); 474 475 first_free_busno=hose->last_busno+1; 476 477 } else { 478 printf (" PCIE: disabled\n"); 479 } 480 } 481 #else 482 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 483 #endif 484 485 } 486 487 int last_stage_init(void) 488 { 489 unsigned short temp; 490 491 /* Change the resistors for the PHY */ 492 /* This is needed to get the RGMII working for the 1.3+ 493 * CDS cards */ 494 if (get_board_version() == 0x13) { 495 miiphy_write(CONFIG_TSEC1_NAME, 496 TSEC1_PHY_ADDR, 29, 18); 497 498 miiphy_read(CONFIG_TSEC1_NAME, 499 TSEC1_PHY_ADDR, 30, &temp); 500 501 temp = (temp & 0xf03f); 502 temp |= 2 << 9; /* 36 ohm */ 503 temp |= 2 << 6; /* 39 ohm */ 504 505 miiphy_write(CONFIG_TSEC1_NAME, 506 TSEC1_PHY_ADDR, 30, temp); 507 508 miiphy_write(CONFIG_TSEC1_NAME, 509 TSEC1_PHY_ADDR, 29, 3); 510 511 miiphy_write(CONFIG_TSEC1_NAME, 512 TSEC1_PHY_ADDR, 30, 0x8000); 513 } 514 515 return 0; 516 } 517 518 519 #if defined(CONFIG_OF_BOARD_SETUP) 520 void 521 ft_pci_setup(void *blob, bd_t *bd) 522 { 523 int node, tmp[2]; 524 const char *path; 525 526 node = fdt_path_offset(blob, "/aliases"); 527 tmp[0] = 0; 528 if (node >= 0) { 529 #ifdef CONFIG_PCI1 530 path = fdt_getprop(blob, node, "pci0", NULL); 531 if (path) { 532 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 533 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 534 } 535 #endif 536 #ifdef CONFIG_PCIE1 537 path = fdt_getprop(blob, node, "pci1", NULL); 538 if (path) { 539 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 540 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 541 } 542 #endif 543 } 544 } 545 #endif 546