1 /* 2 * Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/mmu.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <spd_sdram.h> 33 #include <miiphy.h> 34 #include <libfdt.h> 35 #include <fdt_support.h> 36 37 #include "../common/cadmus.h" 38 #include "../common/eeprom.h" 39 #include "../common/via.h" 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 void local_bus_init(void); 44 void sdram_init(void); 45 46 int checkboard (void) 47 { 48 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 49 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 50 51 /* PCI slot in USER bits CSR[6:7] by convention. */ 52 uint pci_slot = get_pci_slot (); 53 54 uint cpu_board_rev = get_cpu_board_revision (); 55 56 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", 57 get_board_version (), pci_slot); 58 59 printf ("CPU Board Revision %d.%d (0x%04x)\n", 60 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), 61 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); 62 /* 63 * Initialize local bus. 64 */ 65 local_bus_init (); 66 67 /* 68 * Hack TSEC 3 and 4 IO voltages. 69 */ 70 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ 71 72 ecm->eedr = 0xffffffff; /* clear ecm errors */ 73 ecm->eeer = 0xffffffff; /* enable ecm errors */ 74 return 0; 75 } 76 77 phys_size_t 78 initdram(int board_type) 79 { 80 long dram_size = 0; 81 82 puts("Initializing\n"); 83 84 #if defined(CONFIG_DDR_DLL) 85 { 86 /* 87 * Work around to stabilize DDR DLL MSYNC_IN. 88 * Errata DDR9 seems to have been fixed. 89 * This is now the workaround for Errata DDR11: 90 * Override DLL = 1, Course Adj = 1, Tap Select = 0 91 */ 92 93 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 94 95 gur->ddrdllcr = 0x81000000; 96 asm("sync;isync;msync"); 97 udelay(200); 98 } 99 #endif 100 101 dram_size = fsl_ddr_sdram(); 102 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 103 dram_size *= 0x100000; 104 105 /* 106 * SDRAM Initialization 107 */ 108 sdram_init(); 109 110 puts(" DDR: "); 111 return dram_size; 112 } 113 114 /* 115 * Initialize Local Bus 116 */ 117 void 118 local_bus_init(void) 119 { 120 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 121 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 122 123 uint clkdiv; 124 uint lbc_hz; 125 sys_info_t sysinfo; 126 127 get_sys_info(&sysinfo); 128 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 129 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 130 131 gur->lbiuiplldcr1 = 0x00078080; 132 if (clkdiv == 16) { 133 gur->lbiuiplldcr0 = 0x7c0f1bf0; 134 } else if (clkdiv == 8) { 135 gur->lbiuiplldcr0 = 0x6c0f1bf0; 136 } else if (clkdiv == 4) { 137 gur->lbiuiplldcr0 = 0x5c0f1bf0; 138 } 139 140 lbc->lcrr |= 0x00030000; 141 142 asm("sync;isync;msync"); 143 144 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 145 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 146 } 147 148 /* 149 * Initialize SDRAM memory on the Local Bus. 150 */ 151 void 152 sdram_init(void) 153 { 154 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 155 156 uint idx; 157 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 158 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 159 uint cpu_board_rev; 160 uint lsdmr_common; 161 162 puts(" SDRAM: "); 163 164 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 165 166 /* 167 * Setup SDRAM Base and Option Registers 168 */ 169 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 170 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 171 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 172 asm("msync"); 173 174 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 175 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 176 asm("msync"); 177 178 /* 179 * MPC8548 uses "new" 15-16 style addressing. 180 */ 181 cpu_board_rev = get_cpu_board_revision(); 182 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 183 lsdmr_common |= LSDMR_BSMA1516; 184 185 /* 186 * Issue PRECHARGE ALL command. 187 */ 188 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 189 asm("sync;msync"); 190 *sdram_addr = 0xff; 191 ppcDcbf((unsigned long) sdram_addr); 192 udelay(100); 193 194 /* 195 * Issue 8 AUTO REFRESH commands. 196 */ 197 for (idx = 0; idx < 8; idx++) { 198 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 199 asm("sync;msync"); 200 *sdram_addr = 0xff; 201 ppcDcbf((unsigned long) sdram_addr); 202 udelay(100); 203 } 204 205 /* 206 * Issue 8 MODE-set command. 207 */ 208 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 209 asm("sync;msync"); 210 *sdram_addr = 0xff; 211 ppcDcbf((unsigned long) sdram_addr); 212 udelay(100); 213 214 /* 215 * Issue NORMAL OP command. 216 */ 217 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 218 asm("sync;msync"); 219 *sdram_addr = 0xff; 220 ppcDcbf((unsigned long) sdram_addr); 221 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 222 223 #endif /* enable SDRAM init */ 224 } 225 226 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) 227 /* For some reason the Tundra PCI bridge shows up on itself as a 228 * different device. Work around that by refusing to configure it. 229 */ 230 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 231 232 static struct pci_config_table pci_mpc85xxcds_config_table[] = { 233 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 234 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 235 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 236 mpc85xx_config_via_usbide, {0,0,0}}, 237 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 238 mpc85xx_config_via_usb, {0,0,0}}, 239 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 240 mpc85xx_config_via_usb2, {0,0,0}}, 241 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 242 mpc85xx_config_via_power, {0,0,0}}, 243 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 244 mpc85xx_config_via_ac97, {0,0,0}}, 245 {}, 246 }; 247 248 static struct pci_controller pci1_hose = { 249 config_table: pci_mpc85xxcds_config_table}; 250 #endif /* CONFIG_PCI */ 251 252 #ifdef CONFIG_PCI2 253 static struct pci_controller pci2_hose; 254 #endif /* CONFIG_PCI2 */ 255 256 #ifdef CONFIG_PCIE1 257 static struct pci_controller pcie1_hose; 258 #endif /* CONFIG_PCIE1 */ 259 260 void pci_init_board(void) 261 { 262 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 263 struct fsl_pci_info pci_info[4]; 264 u32 devdisr, pordevsr, io_sel; 265 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 266 int first_free_busno = 0; 267 int num = 0; 268 269 int pcie_ep, pcie_configured; 270 271 devdisr = in_be32(&gur->devdisr); 272 pordevsr = in_be32(&gur->pordevsr); 273 porpllsr = in_be32(&gur->porpllsr); 274 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 275 276 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 277 278 #ifdef CONFIG_PCI1 279 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 280 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ 281 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 282 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 283 284 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 285 SET_STD_PCI_INFO(pci_info[num], 1); 286 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 287 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 288 (pci_32) ? 32 : 64, 289 (pci_speed == 33333000) ? "33" : 290 (pci_speed == 66666000) ? "66" : "unknown", 291 pci_clk_sel ? "sync" : "async", 292 pci_agent ? "agent" : "host", 293 pci_arb ? "arbiter" : "external-arbiter", 294 pci_info[num].regs); 295 296 first_free_busno = fsl_pci_init_port(&pci_info[num++], 297 &pci1_hose, first_free_busno); 298 299 #ifdef CONFIG_PCIX_CHECK 300 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) { 301 /* PCI-X init */ 302 if (CONFIG_SYS_CLK_FREQ < 66000000) 303 printf("PCI-X will only work at 66 MHz\n"); 304 305 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 306 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 307 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); 308 } 309 #endif 310 } else { 311 printf (" PCI: disabled\n"); 312 } 313 314 puts("\n"); 315 #else 316 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 317 #endif 318 319 #ifdef CONFIG_PCI2 320 { 321 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ 322 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 323 if (pci_dual) { 324 printf (" PCI2: 32 bit, 66 MHz, %s\n", 325 pci2_clk_sel ? "sync" : "async"); 326 } else { 327 printf (" PCI2: disabled\n"); 328 } 329 } 330 #else 331 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ 332 #endif /* CONFIG_PCI2 */ 333 334 #ifdef CONFIG_PCIE1 335 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 336 337 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 338 SET_STD_PCIE_INFO(pci_info[num], 1); 339 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 340 printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", 341 pcie_ep ? "Endpoint" : "Root Complex", 342 pci_info[num].regs); 343 344 first_free_busno = fsl_pci_init_port(&pci_info[num++], 345 &pcie1_hose, first_free_busno); 346 } else { 347 printf (" PCIE1: disabled\n"); 348 } 349 350 puts("\n"); 351 #else 352 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 353 #endif 354 } 355 356 int last_stage_init(void) 357 { 358 unsigned short temp; 359 360 /* Change the resistors for the PHY */ 361 /* This is needed to get the RGMII working for the 1.3+ 362 * CDS cards */ 363 if (get_board_version() == 0x13) { 364 miiphy_write(CONFIG_TSEC1_NAME, 365 TSEC1_PHY_ADDR, 29, 18); 366 367 miiphy_read(CONFIG_TSEC1_NAME, 368 TSEC1_PHY_ADDR, 30, &temp); 369 370 temp = (temp & 0xf03f); 371 temp |= 2 << 9; /* 36 ohm */ 372 temp |= 2 << 6; /* 39 ohm */ 373 374 miiphy_write(CONFIG_TSEC1_NAME, 375 TSEC1_PHY_ADDR, 30, temp); 376 377 miiphy_write(CONFIG_TSEC1_NAME, 378 TSEC1_PHY_ADDR, 29, 3); 379 380 miiphy_write(CONFIG_TSEC1_NAME, 381 TSEC1_PHY_ADDR, 30, 0x8000); 382 } 383 384 return 0; 385 } 386 387 388 #if defined(CONFIG_OF_BOARD_SETUP) 389 void ft_pci_setup(void *blob, bd_t *bd) 390 { 391 FT_FSL_PCI_SETUP; 392 } 393 #endif 394