1 /*
2  * Copyright 2004, 2007 Freescale Semiconductor.
3  *
4  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #include <common.h>
26 #include <pci.h>
27 #include <asm/processor.h>
28 #include <asm/mmu.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/immap_fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <spd_sdram.h>
33 #include <miiphy.h>
34 #include <libfdt.h>
35 #include <fdt_support.h>
36 
37 #include "../common/cadmus.h"
38 #include "../common/eeprom.h"
39 #include "../common/via.h"
40 
41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
42 extern void ddr_enable_ecc(unsigned int dram_size);
43 #endif
44 
45 DECLARE_GLOBAL_DATA_PTR;
46 
47 void local_bus_init(void);
48 void sdram_init(void);
49 
50 int checkboard (void)
51 {
52 	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
53 	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
54 
55 	/* PCI slot in USER bits CSR[6:7] by convention. */
56 	uint pci_slot = get_pci_slot ();
57 
58 	uint cpu_board_rev = get_cpu_board_revision ();
59 	uint svr;
60 
61 	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
62 		get_board_version (), pci_slot);
63 
64 	printf ("CPU Board Revision %d.%d (0x%04x)\n",
65 		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
66 		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
67 	/*
68 	 * Initialize local bus.
69 	 */
70 	local_bus_init ();
71 
72 	svr = get_svr();
73 
74 	/*
75 	 * Fix CPU2 errata: A core hang possible while executing a
76 	 * msync instruction and a snoopable transaction from an I/O
77 	 * master tagged to make quick forward progress is present.
78 	 * Fixed in Silicon Rev.2.1
79 	 */
80 	if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
81 		ecm->eebpcr |= (1 << 16);
82 
83 	/*
84 	 * Hack TSEC 3 and 4 IO voltages.
85 	 */
86 	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */
87 
88 	ecm->eedr = 0xffffffff;		/* clear ecm errors */
89 	ecm->eeer = 0xffffffff;		/* enable ecm errors */
90 	return 0;
91 }
92 
93 phys_size_t
94 initdram(int board_type)
95 {
96 	long dram_size = 0;
97 
98 	puts("Initializing\n");
99 
100 #if defined(CONFIG_DDR_DLL)
101 	{
102 		/*
103 		 * Work around to stabilize DDR DLL MSYNC_IN.
104 		 * Errata DDR9 seems to have been fixed.
105 		 * This is now the workaround for Errata DDR11:
106 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
107 		 */
108 
109 		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
110 
111 		gur->ddrdllcr = 0x81000000;
112 		asm("sync;isync;msync");
113 		udelay(200);
114 	}
115 #endif
116 
117 	dram_size = fsl_ddr_sdram();
118 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
119 	dram_size *= 0x100000;
120 
121 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
122 	/*
123 	 * Initialize and enable DDR ECC.
124 	 */
125 	ddr_enable_ecc(dram_size);
126 #endif
127 
128 	/*
129 	 * SDRAM Initialization
130 	 */
131 	sdram_init();
132 
133 	puts("    DDR: ");
134 	return dram_size;
135 }
136 
137 /*
138  * Initialize Local Bus
139  */
140 void
141 local_bus_init(void)
142 {
143 	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
144 	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
145 
146 	uint clkdiv;
147 	uint lbc_hz;
148 	sys_info_t sysinfo;
149 
150 	get_sys_info(&sysinfo);
151 	clkdiv = (lbc->lcrr & 0x0f) * 2;
152 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
153 
154 	gur->lbiuiplldcr1 = 0x00078080;
155 	if (clkdiv == 16) {
156 		gur->lbiuiplldcr0 = 0x7c0f1bf0;
157 	} else if (clkdiv == 8) {
158 		gur->lbiuiplldcr0 = 0x6c0f1bf0;
159 	} else if (clkdiv == 4) {
160 		gur->lbiuiplldcr0 = 0x5c0f1bf0;
161 	}
162 
163 	lbc->lcrr |= 0x00030000;
164 
165 	asm("sync;isync;msync");
166 
167 	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
168 	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
169 }
170 
171 /*
172  * Initialize SDRAM memory on the Local Bus.
173  */
174 void
175 sdram_init(void)
176 {
177 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
178 
179 	uint idx;
180 	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
181 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
182 	uint cpu_board_rev;
183 	uint lsdmr_common;
184 
185 	puts("    SDRAM: ");
186 
187 	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
188 
189 	/*
190 	 * Setup SDRAM Base and Option Registers
191 	 */
192 	lbc->or2 = CFG_OR2_PRELIM;
193 	asm("msync");
194 
195 	lbc->br2 = CFG_BR2_PRELIM;
196 	asm("msync");
197 
198 	lbc->lbcr = CFG_LBC_LBCR;
199 	asm("msync");
200 
201 
202 	lbc->lsrt = CFG_LBC_LSRT;
203 	lbc->mrtpr = CFG_LBC_MRTPR;
204 	asm("msync");
205 
206 	/*
207 	 * MPC8548 uses "new" 15-16 style addressing.
208 	 */
209 	cpu_board_rev = get_cpu_board_revision();
210 	lsdmr_common = CFG_LBC_LSDMR_COMMON;
211 	lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
212 
213 	/*
214 	 * Issue PRECHARGE ALL command.
215 	 */
216 	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
217 	asm("sync;msync");
218 	*sdram_addr = 0xff;
219 	ppcDcbf((unsigned long) sdram_addr);
220 	udelay(100);
221 
222 	/*
223 	 * Issue 8 AUTO REFRESH commands.
224 	 */
225 	for (idx = 0; idx < 8; idx++) {
226 		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
227 		asm("sync;msync");
228 		*sdram_addr = 0xff;
229 		ppcDcbf((unsigned long) sdram_addr);
230 		udelay(100);
231 	}
232 
233 	/*
234 	 * Issue 8 MODE-set command.
235 	 */
236 	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
237 	asm("sync;msync");
238 	*sdram_addr = 0xff;
239 	ppcDcbf((unsigned long) sdram_addr);
240 	udelay(100);
241 
242 	/*
243 	 * Issue NORMAL OP command.
244 	 */
245 	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
246 	asm("sync;msync");
247 	*sdram_addr = 0xff;
248 	ppcDcbf((unsigned long) sdram_addr);
249 	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
250 
251 #endif	/* enable SDRAM init */
252 }
253 
254 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
255 /* For some reason the Tundra PCI bridge shows up on itself as a
256  * different device.  Work around that by refusing to configure it.
257  */
258 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
259 
260 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
261 	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
262 	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
263 	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
264 		mpc85xx_config_via_usbide, {0,0,0}},
265 	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
266 		mpc85xx_config_via_usb, {0,0,0}},
267 	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
268 		mpc85xx_config_via_usb2, {0,0,0}},
269 	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
270 		mpc85xx_config_via_power, {0,0,0}},
271 	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
272 		mpc85xx_config_via_ac97, {0,0,0}},
273 	{},
274 };
275 
276 static struct pci_controller pci1_hose = {
277 	config_table: pci_mpc85xxcds_config_table};
278 #endif	/* CONFIG_PCI */
279 
280 #ifdef CONFIG_PCI2
281 static struct pci_controller pci2_hose;
282 #endif	/* CONFIG_PCI2 */
283 
284 #ifdef CONFIG_PCIE1
285 static struct pci_controller pcie1_hose;
286 #endif	/* CONFIG_PCIE1 */
287 
288 int first_free_busno=0;
289 
290 void
291 pci_init_board(void)
292 {
293 	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
294 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
295 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
296 
297 
298 #ifdef CONFIG_PCI1
299 {
300 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
301 	extern void fsl_pci_init(struct pci_controller *hose);
302 	struct pci_controller *hose = &pci1_hose;
303 	struct pci_config_table *table;
304 
305 	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
306 	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
307 	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */
308 
309 	uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
310 
311 	uint pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
312 
313 	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
314 		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
315 			(pci_32) ? 32 : 64,
316 			(pci_speed == 33333000) ? "33" :
317 			(pci_speed == 66666000) ? "66" : "unknown",
318 			pci_clk_sel ? "sync" : "async",
319 			pci_agent ? "agent" : "host",
320 			pci_arb ? "arbiter" : "external-arbiter"
321 			);
322 
323 
324 		/* inbound */
325 		pci_set_region(hose->regions + 0,
326 			       CFG_PCI_MEMORY_BUS,
327 			       CFG_PCI_MEMORY_PHYS,
328 			       CFG_PCI_MEMORY_SIZE,
329 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
330 
331 
332 		/* outbound memory */
333 		pci_set_region(hose->regions + 1,
334 			       CFG_PCI1_MEM_BASE,
335 			       CFG_PCI1_MEM_PHYS,
336 			       CFG_PCI1_MEM_SIZE,
337 			       PCI_REGION_MEM);
338 
339 		/* outbound io */
340 		pci_set_region(hose->regions + 2,
341 			       CFG_PCI1_IO_BASE,
342 			       CFG_PCI1_IO_PHYS,
343 			       CFG_PCI1_IO_SIZE,
344 			       PCI_REGION_IO);
345 		hose->region_count = 3;
346 
347 		/* relocate config table pointers */
348 		hose->config_table = \
349 			(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
350 		for (table = hose->config_table; table && table->vendor; table++)
351 			table->config_device += gd->reloc_off;
352 
353 		hose->first_busno=first_free_busno;
354 		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
355 
356 		fsl_pci_init(hose);
357 		first_free_busno=hose->last_busno+1;
358 		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
359 #ifdef CONFIG_PCIX_CHECK
360 		if (!(gur->pordevsr & PORDEVSR_PCI)) {
361 			/* PCI-X init */
362 			if (CONFIG_SYS_CLK_FREQ < 66000000)
363 				printf("PCI-X will only work at 66 MHz\n");
364 
365 			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
366 				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
367 			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
368 		}
369 #endif
370 	} else {
371 		printf ("    PCI: disabled\n");
372 	}
373 }
374 #else
375 	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
376 #endif
377 
378 #ifdef CONFIG_PCI2
379 {
380 	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
381 	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
382 	if (pci_dual) {
383 		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
384 			pci2_clk_sel ? "sync" : "async");
385 	} else {
386 		printf ("    PCI2: disabled\n");
387 	}
388 }
389 #else
390 	gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
391 #endif /* CONFIG_PCI2 */
392 
393 #ifdef CONFIG_PCIE1
394 {
395 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
396 	extern void fsl_pci_init(struct pci_controller *hose);
397 	struct pci_controller *hose = &pcie1_hose;
398 	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
399 
400 	int pcie_configured  = io_sel >= 1;
401 
402 	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
403 		printf ("\n    PCIE connected to slot as %s (base address %x)",
404 			pcie_ep ? "End Point" : "Root Complex",
405 			(uint)pci);
406 
407 		if (pci->pme_msg_det) {
408 			pci->pme_msg_det = 0xffffffff;
409 			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
410 		}
411 		printf ("\n");
412 
413 		/* inbound */
414 		pci_set_region(hose->regions + 0,
415 			       CFG_PCI_MEMORY_BUS,
416 			       CFG_PCI_MEMORY_PHYS,
417 			       CFG_PCI_MEMORY_SIZE,
418 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
419 
420 		/* outbound memory */
421 		pci_set_region(hose->regions + 1,
422 			       CFG_PCIE1_MEM_BASE,
423 			       CFG_PCIE1_MEM_PHYS,
424 			       CFG_PCIE1_MEM_SIZE,
425 			       PCI_REGION_MEM);
426 
427 		/* outbound io */
428 		pci_set_region(hose->regions + 2,
429 			       CFG_PCIE1_IO_BASE,
430 			       CFG_PCIE1_IO_PHYS,
431 			       CFG_PCIE1_IO_SIZE,
432 			       PCI_REGION_IO);
433 
434 		hose->region_count = 3;
435 
436 		hose->first_busno=first_free_busno;
437 		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
438 
439 		fsl_pci_init(hose);
440 		printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
441 
442 		first_free_busno=hose->last_busno+1;
443 
444 	} else {
445 		printf ("    PCIE: disabled\n");
446 	}
447  }
448 #else
449 	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
450 #endif
451 
452 }
453 
454 int last_stage_init(void)
455 {
456 	unsigned short temp;
457 
458 	/* Change the resistors for the PHY */
459 	/* This is needed to get the RGMII working for the 1.3+
460 	 * CDS cards */
461 	if (get_board_version() ==  0x13) {
462 		miiphy_write(CONFIG_TSEC1_NAME,
463 				TSEC1_PHY_ADDR, 29, 18);
464 
465 		miiphy_read(CONFIG_TSEC1_NAME,
466 				TSEC1_PHY_ADDR, 30, &temp);
467 
468 		temp = (temp & 0xf03f);
469 		temp |= 2 << 9;		/* 36 ohm */
470 		temp |= 2 << 6;		/* 39 ohm */
471 
472 		miiphy_write(CONFIG_TSEC1_NAME,
473 				TSEC1_PHY_ADDR, 30, temp);
474 
475 		miiphy_write(CONFIG_TSEC1_NAME,
476 				TSEC1_PHY_ADDR, 29, 3);
477 
478 		miiphy_write(CONFIG_TSEC1_NAME,
479 				TSEC1_PHY_ADDR, 30, 0x8000);
480 	}
481 
482 	return 0;
483 }
484 
485 
486 #if defined(CONFIG_OF_BOARD_SETUP)
487 void
488 ft_pci_setup(void *blob, bd_t *bd)
489 {
490 	int node, tmp[2];
491 	const char *path;
492 
493 	node = fdt_path_offset(blob, "/aliases");
494 	tmp[0] = 0;
495 	if (node >= 0) {
496 #ifdef CONFIG_PCI1
497 		path = fdt_getprop(blob, node, "pci0", NULL);
498 		if (path) {
499 			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
500 			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
501 		}
502 #endif
503 #ifdef CONFIG_PCIE1
504 		path = fdt_getprop(blob, node, "pci1", NULL);
505 		if (path) {
506 			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
507 			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
508 		}
509 #endif
510 	}
511 }
512 #endif
513