12cfaa1aaSKumar Gala /*
22cfaa1aaSKumar Gala  * Copyright 2008 Freescale Semiconductor, Inc.
32cfaa1aaSKumar Gala  *
42cfaa1aaSKumar Gala  * (C) Copyright 2000
52cfaa1aaSKumar Gala  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
62cfaa1aaSKumar Gala  *
72cfaa1aaSKumar Gala  * See file CREDITS for list of people who contributed to this
82cfaa1aaSKumar Gala  * project.
92cfaa1aaSKumar Gala  *
102cfaa1aaSKumar Gala  * This program is free software; you can redistribute it and/or
112cfaa1aaSKumar Gala  * modify it under the terms of the GNU General Public License as
122cfaa1aaSKumar Gala  * published by the Free Software Foundation; either version 2 of
132cfaa1aaSKumar Gala  * the License, or (at your option) any later version.
142cfaa1aaSKumar Gala  *
152cfaa1aaSKumar Gala  * This program is distributed in the hope that it will be useful,
162cfaa1aaSKumar Gala  * but WITHOUT ANY WARRANTY; without even the implied warranty of
172cfaa1aaSKumar Gala  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
182cfaa1aaSKumar Gala  * GNU General Public License for more details.
192cfaa1aaSKumar Gala  *
202cfaa1aaSKumar Gala  * You should have received a copy of the GNU General Public License
212cfaa1aaSKumar Gala  * along with this program; if not, write to the Free Software
222cfaa1aaSKumar Gala  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
232cfaa1aaSKumar Gala  * MA 02111-1307 USA
242cfaa1aaSKumar Gala  */
252cfaa1aaSKumar Gala 
262cfaa1aaSKumar Gala #include <common.h>
272cfaa1aaSKumar Gala #include <asm/fsl_law.h>
282cfaa1aaSKumar Gala #include <asm/mmu.h>
292cfaa1aaSKumar Gala 
302cfaa1aaSKumar Gala /*
312cfaa1aaSKumar Gala  * LAW(Local Access Window) configuration:
322cfaa1aaSKumar Gala  *
332cfaa1aaSKumar Gala  * 0x0000_0000     0x7fff_ffff     DDR                     2G
342cfaa1aaSKumar Gala  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
352cfaa1aaSKumar Gala  * 0xa000_0000     0xbfff_ffff     PCIe MEM                512M
362cfaa1aaSKumar Gala  * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
372cfaa1aaSKumar Gala  * 0xe000_0000     0xe000_ffff     CCSR                    1M
382cfaa1aaSKumar Gala  * 0xe200_0000     0xe10f_ffff     PCI1 IO                 1M
392cfaa1aaSKumar Gala  * 0xe280_0000     0xe20f_ffff     PCI2 IO                 1M
402cfaa1aaSKumar Gala  * 0xe300_0000     0xe30f_ffff     PCIe IO                 1M
412cfaa1aaSKumar Gala  * 0xf000_0000     0xf3ff_ffff     SDRAM                   64M
422cfaa1aaSKumar Gala  * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
432cfaa1aaSKumar Gala  * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
442cfaa1aaSKumar Gala  * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
452cfaa1aaSKumar Gala  *
462cfaa1aaSKumar Gala  * Notes:
472cfaa1aaSKumar Gala  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
482cfaa1aaSKumar Gala  *    If flash is 8M at default position (last 8M), no LAW needed.
492cfaa1aaSKumar Gala  *
502cfaa1aaSKumar Gala  * LAW 0 is reserved for boot mapping
512cfaa1aaSKumar Gala  */
522cfaa1aaSKumar Gala 
532cfaa1aaSKumar Gala struct law_entry law_table[] = {
54*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_PCI1_MEM_PHYS
55*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
56*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
572cfaa1aaSKumar Gala #endif
58*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_PCI2_MEM_PHYS
59*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
60*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
612cfaa1aaSKumar Gala #endif
62*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_PCIE1_MEM_PHYS
63*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
64*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
652cfaa1aaSKumar Gala #endif
662cfaa1aaSKumar Gala 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
67*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
68*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_RIO_MEM_PHYS
69*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
702cfaa1aaSKumar Gala #endif
712cfaa1aaSKumar Gala };
722cfaa1aaSKumar Gala 
732cfaa1aaSKumar Gala int num_law_entries = ARRAY_SIZE(law_table);
74