1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/mmu.h> 12 13 struct fsl_e_tlb_entry tlb_table[] = { 14 /* TLB 0 - for temp stack in cache */ 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 16 MAS3_SX|MAS3_SW|MAS3_SR, 0, 17 0, 0, BOOKE_PAGESZ_4K, 0), 18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19 MAS3_SX|MAS3_SW|MAS3_SR, 0, 20 0, 0, BOOKE_PAGESZ_4K, 0), 21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22 MAS3_SX|MAS3_SW|MAS3_SR, 0, 23 0, 0, BOOKE_PAGESZ_4K, 0), 24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 26 0, 0, BOOKE_PAGESZ_4K, 0), 27 /* 28 * TLB 0: 64M Non-cacheable, guarded 29 * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000 30 * Out of reset this entry is only 4K. 31 */ 32 SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK, 33 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 34 0, 0, BOOKE_PAGESZ_64M, 1), 35 /* 36 * TLB 1: 1G Non-cacheable, guarded 37 * 0x80000000 1G PCIE 8,9,a,b 38 */ 39 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS, 40 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 41 0, 1, BOOKE_PAGESZ_1G, 1), 42 43 /* 44 * TLB 2: 256M Non-cacheable, guarded 45 */ 46 SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS, 47 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 48 0, 2, BOOKE_PAGESZ_256M, 1), 49 50 /* 51 * TLB 3: 256M Non-cacheable, guarded 52 */ 53 SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000, 54 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 55 0, 3, BOOKE_PAGESZ_256M, 1), 56 57 /* 58 * TLB 4: 64M Non-cacheable, guarded 59 * 0xe000_0000 1M CCSRBAR 60 * 0xe100_0000 255M PCI IO range 61 */ 62 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 63 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64 0, 4, BOOKE_PAGESZ_64M, 1), 65 66 /* 67 * TLB 5: 64M Non-cacheable, guarded 68 * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF 69 */ 70 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE, 71 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 72 0, 5, BOOKE_PAGESZ_64M, 1), 73 }; 74 75 int num_tlb_entries = ARRAY_SIZE(tlb_table); 76