1 /* 2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/fsl_pci.h> 30 #include <asm/fsl_ddr_sdram.h> 31 #include <asm/fsl_serdes.h> 32 #include <asm/io.h> 33 #include <miiphy.h> 34 #include <libfdt.h> 35 #include <fdt_support.h> 36 #include <tsec.h> 37 #include <netdev.h> 38 39 #include "../common/sgmii_riser.h" 40 41 int checkboard (void) 42 { 43 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 44 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 45 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 46 u8 vboot; 47 u8 *pixis_base = (u8 *)PIXIS_BASE; 48 49 if ((uint)&gur->porpllsr != 0xe00e0000) { 50 printf("immap size error %lx\n",(ulong)&gur->porpllsr); 51 } 52 printf ("Board: MPC8544DS, Sys ID: 0x%02x, " 53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 54 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 55 in_8(pixis_base + PIXIS_PVER)); 56 57 vboot = in_8(pixis_base + PIXIS_VBOOT); 58 if (vboot & PIXIS_VBOOT_FMAP) 59 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); 60 else 61 puts ("Promjet\n"); 62 63 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 64 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 65 ecm->eedr = 0xffffffff; /* Clear ecm errors */ 66 ecm->eeer = 0xffffffff; /* Enable ecm errors */ 67 68 return 0; 69 } 70 71 #ifdef CONFIG_PCI1 72 static struct pci_controller pci1_hose; 73 #endif 74 75 #ifdef CONFIG_PCIE3 76 static struct pci_controller pcie3_hose; 77 #endif 78 79 void pci_init_board(void) 80 { 81 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 82 struct fsl_pci_info pci_info; 83 u32 devdisr, pordevsr, io_sel; 84 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 85 int first_free_busno = 0; 86 87 int pcie_ep, pcie_configured; 88 89 devdisr = in_be32(&gur->devdisr); 90 pordevsr = in_be32(&gur->pordevsr); 91 porpllsr = in_be32(&gur->porpllsr); 92 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 93 94 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 95 96 puts("\n"); 97 98 #ifdef CONFIG_PCIE3 99 pcie_configured = is_serdes_configured(PCIE3); 100 101 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 102 /* contains both PCIE3 MEM & IO space */ 103 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, 104 LAW_TRGT_IF_PCIE_3); 105 SET_STD_PCIE_INFO(pci_info, 3); 106 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs); 107 108 /* outbound memory */ 109 pci_set_region(&pcie3_hose.regions[0], 110 CONFIG_SYS_PCIE3_MEM_BUS2, 111 CONFIG_SYS_PCIE3_MEM_PHYS2, 112 CONFIG_SYS_PCIE3_MEM_SIZE2, 113 PCI_REGION_MEM); 114 115 pcie3_hose.region_count = 1; 116 117 printf("PCIE3: connected to ULI as %s (base addr %lx)\n", 118 pcie_ep ? "Endpoint" : "Root Complex", 119 pci_info.regs); 120 first_free_busno = fsl_pci_init_port(&pci_info, 121 &pcie3_hose, first_free_busno); 122 123 /* 124 * Activate ULI1575 legacy chip by performing a fake 125 * memory access. Needed to make ULI RTC work. 126 */ 127 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); 128 } else { 129 printf("PCIE3: disabled\n"); 130 } 131 puts("\n"); 132 #else 133 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 134 #endif 135 136 #ifdef CONFIG_PCIE1 137 SET_STD_PCIE_INFO(pci_info, 1); 138 first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info); 139 #else 140 setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ 141 #endif 142 143 #ifdef CONFIG_PCIE2 144 SET_STD_PCIE_INFO(pci_info, 2); 145 first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info); 146 #else 147 setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ 148 #endif 149 150 #ifdef CONFIG_PCI1 151 pci_speed = 66666000; 152 pci_32 = 1; 153 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 154 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 155 156 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 157 SET_STD_PCI_INFO(pci_info, 1); 158 set_next_law(pci_info.mem_phys, 159 law_size_bits(pci_info.mem_size), pci_info.law); 160 set_next_law(pci_info.io_phys, 161 law_size_bits(pci_info.io_size), pci_info.law); 162 163 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 164 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 165 (pci_32) ? 32 : 64, 166 (pci_speed == 33333000) ? "33" : 167 (pci_speed == 66666000) ? "66" : "unknown", 168 pci_clk_sel ? "sync" : "async", 169 pci_agent ? "agent" : "host", 170 pci_arb ? "arbiter" : "external-arbiter", 171 pci_info.regs); 172 173 first_free_busno = fsl_pci_init_port(&pci_info, 174 &pci1_hose, first_free_busno); 175 } else { 176 printf("PCI: disabled\n"); 177 } 178 179 puts("\n"); 180 #else 181 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 182 #endif 183 } 184 185 int last_stage_init(void) 186 { 187 return 0; 188 } 189 190 191 unsigned long 192 get_board_sys_clk(ulong dummy) 193 { 194 u8 i, go_bit, rd_clks; 195 ulong val = 0; 196 u8 *pixis_base = (u8 *)PIXIS_BASE; 197 198 go_bit = in_8(pixis_base + PIXIS_VCTL); 199 go_bit &= 0x01; 200 201 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); 202 rd_clks &= 0x1C; 203 204 /* 205 * Only if both go bit and the SCLK bit in VCFGEN0 are set 206 * should we be using the AUX register. Remember, we also set the 207 * GO bit to boot from the alternate bank on the on-board flash 208 */ 209 210 if (go_bit) { 211 if (rd_clks == 0x1c) 212 i = in_8(pixis_base + PIXIS_AUX); 213 else 214 i = in_8(pixis_base + PIXIS_SPD); 215 } else { 216 i = in_8(pixis_base + PIXIS_SPD); 217 } 218 219 i &= 0x07; 220 221 switch (i) { 222 case 0: 223 val = 33333333; 224 break; 225 case 1: 226 val = 40000000; 227 break; 228 case 2: 229 val = 50000000; 230 break; 231 case 3: 232 val = 66666666; 233 break; 234 case 4: 235 val = 83000000; 236 break; 237 case 5: 238 val = 100000000; 239 break; 240 case 6: 241 val = 133333333; 242 break; 243 case 7: 244 val = 166666666; 245 break; 246 } 247 248 return val; 249 } 250 251 int board_eth_init(bd_t *bis) 252 { 253 #ifdef CONFIG_TSEC_ENET 254 struct tsec_info_struct tsec_info[2]; 255 int num = 0; 256 257 #ifdef CONFIG_TSEC1 258 SET_STD_TSEC_INFO(tsec_info[num], 1); 259 if (is_serdes_configured(SGMII_TSEC1)) { 260 puts("eTSEC1 is in sgmii mode.\n"); 261 tsec_info[num].flags |= TSEC_SGMII; 262 } 263 num++; 264 #endif 265 #ifdef CONFIG_TSEC3 266 SET_STD_TSEC_INFO(tsec_info[num], 3); 267 if (is_serdes_configured(SGMII_TSEC3)) { 268 puts("eTSEC3 is in sgmii mode.\n"); 269 tsec_info[num].flags |= TSEC_SGMII; 270 } 271 num++; 272 #endif 273 274 if (!num) { 275 printf("No TSECs initialized\n"); 276 277 return 0; 278 } 279 280 if (is_serdes_configured(SGMII_TSEC1) || 281 is_serdes_configured(SGMII_TSEC3)) { 282 fsl_sgmii_riser_init(tsec_info, num); 283 } 284 285 286 tsec_eth_init(bis, tsec_info, num); 287 #endif 288 return pci_eth_init(bis); 289 } 290 291 #if defined(CONFIG_OF_BOARD_SETUP) 292 void ft_board_setup(void *blob, bd_t *bd) 293 { 294 ft_cpu_setup(blob, bd); 295 296 FT_FSL_PCI_SETUP; 297 298 #ifdef CONFIG_FSL_SGMII_RISER 299 fsl_sgmii_riser_fdt_fixup(blob); 300 #endif 301 } 302 #endif 303