1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/fsl_pci.h> 30 #include <asm/fsl_ddr_sdram.h> 31 #include <asm/io.h> 32 #include <miiphy.h> 33 #include <libfdt.h> 34 #include <fdt_support.h> 35 #include <tsec.h> 36 #include <netdev.h> 37 38 #include "../common/pixis.h" 39 #include "../common/sgmii_riser.h" 40 41 int checkboard (void) 42 { 43 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 44 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 45 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 46 47 if ((uint)&gur->porpllsr != 0xe00e0000) { 48 printf("immap size error %lx\n",(ulong)&gur->porpllsr); 49 } 50 printf ("Board: MPC8544DS, System ID: 0x%02x, " 51 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 52 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 53 in8(PIXIS_BASE + PIXIS_PVER)); 54 55 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 56 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 57 ecm->eedr = 0xffffffff; /* Clear ecm errors */ 58 ecm->eeer = 0xffffffff; /* Enable ecm errors */ 59 60 return 0; 61 } 62 63 phys_size_t 64 initdram(int board_type) 65 { 66 long dram_size = 0; 67 68 puts("Initializing\n"); 69 70 dram_size = fsl_ddr_sdram(); 71 72 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 73 74 dram_size *= 0x100000; 75 76 puts(" DDR: "); 77 return dram_size; 78 } 79 80 #ifdef CONFIG_PCI1 81 static struct pci_controller pci1_hose; 82 #endif 83 84 #ifdef CONFIG_PCIE1 85 static struct pci_controller pcie1_hose; 86 #endif 87 88 #ifdef CONFIG_PCIE2 89 static struct pci_controller pcie2_hose; 90 #endif 91 92 #ifdef CONFIG_PCIE3 93 static struct pci_controller pcie3_hose; 94 #endif 95 96 int first_free_busno=0; 97 98 void 99 pci_init_board(void) 100 { 101 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 102 uint devdisr = gur->devdisr; 103 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 104 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 105 106 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 107 devdisr, io_sel, host_agent); 108 109 if (io_sel & 1) { 110 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 111 printf (" eTSEC1 is in sgmii mode.\n"); 112 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 113 printf (" eTSEC3 is in sgmii mode.\n"); 114 } 115 116 #ifdef CONFIG_PCIE3 117 { 118 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 119 struct pci_controller *hose = &pcie3_hose; 120 int pcie_ep = (host_agent == 1); 121 int pcie_configured = io_sel >= 6; 122 struct pci_region *r = hose->regions; 123 124 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 125 printf ("\n PCIE3 connected to ULI as %s (base address %x)", 126 pcie_ep ? "End Point" : "Root Complex", 127 (uint)pci); 128 if (pci->pme_msg_det) { 129 pci->pme_msg_det = 0xffffffff; 130 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 131 } 132 printf ("\n"); 133 134 /* inbound */ 135 r += fsl_pci_setup_inbound_windows(r); 136 137 /* outbound memory */ 138 pci_set_region(r++, 139 CONFIG_SYS_PCIE3_MEM_BUS, 140 CONFIG_SYS_PCIE3_MEM_PHYS, 141 CONFIG_SYS_PCIE3_MEM_SIZE, 142 PCI_REGION_MEM); 143 144 /* outbound io */ 145 pci_set_region(r++, 146 CONFIG_SYS_PCIE3_IO_BUS, 147 CONFIG_SYS_PCIE3_IO_PHYS, 148 CONFIG_SYS_PCIE3_IO_SIZE, 149 PCI_REGION_IO); 150 151 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2 152 /* outbound memory */ 153 pci_set_region(r++, 154 CONFIG_SYS_PCIE3_MEM_BUS2, 155 CONFIG_SYS_PCIE3_MEM_PHYS2, 156 CONFIG_SYS_PCIE3_MEM_SIZE2, 157 PCI_REGION_MEM); 158 #endif 159 hose->region_count = r - hose->regions; 160 hose->first_busno=first_free_busno; 161 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 162 163 fsl_pci_init(hose); 164 165 first_free_busno=hose->last_busno+1; 166 printf (" PCIE3 on bus %02x - %02x\n", 167 hose->first_busno,hose->last_busno); 168 169 /* 170 * Activate ULI1575 legacy chip by performing a fake 171 * memory access. Needed to make ULI RTC work. 172 */ 173 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); 174 } else { 175 printf (" PCIE3: disabled\n"); 176 } 177 178 } 179 #else 180 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 181 #endif 182 183 #ifdef CONFIG_PCIE1 184 { 185 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 186 struct pci_controller *hose = &pcie1_hose; 187 int pcie_ep = (host_agent == 5); 188 int pcie_configured = io_sel >= 2; 189 struct pci_region *r = hose->regions; 190 191 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 192 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", 193 pcie_ep ? "End Point" : "Root Complex", 194 (uint)pci); 195 if (pci->pme_msg_det) { 196 pci->pme_msg_det = 0xffffffff; 197 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 198 } 199 printf ("\n"); 200 201 /* inbound */ 202 r += fsl_pci_setup_inbound_windows(r); 203 204 /* outbound memory */ 205 pci_set_region(r++, 206 CONFIG_SYS_PCIE1_MEM_BUS, 207 CONFIG_SYS_PCIE1_MEM_PHYS, 208 CONFIG_SYS_PCIE1_MEM_SIZE, 209 PCI_REGION_MEM); 210 211 /* outbound io */ 212 pci_set_region(r++, 213 CONFIG_SYS_PCIE1_IO_BUS, 214 CONFIG_SYS_PCIE1_IO_PHYS, 215 CONFIG_SYS_PCIE1_IO_SIZE, 216 PCI_REGION_IO); 217 218 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 219 /* outbound memory */ 220 pci_set_region(r++, 221 CONFIG_SYS_PCIE1_MEM_BUS2, 222 CONFIG_SYS_PCIE1_MEM_PHYS2, 223 CONFIG_SYS_PCIE1_MEM_SIZE2, 224 PCI_REGION_MEM); 225 #endif 226 hose->region_count = r - hose->regions; 227 hose->first_busno=first_free_busno; 228 229 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 230 231 fsl_pci_init(hose); 232 233 first_free_busno=hose->last_busno+1; 234 printf(" PCIE1 on bus %02x - %02x\n", 235 hose->first_busno,hose->last_busno); 236 237 } else { 238 printf (" PCIE1: disabled\n"); 239 } 240 241 } 242 #else 243 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 244 #endif 245 246 #ifdef CONFIG_PCIE2 247 { 248 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 249 struct pci_controller *hose = &pcie2_hose; 250 int pcie_ep = (host_agent == 3); 251 int pcie_configured = io_sel >= 4; 252 struct pci_region *r = hose->regions; 253 254 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 255 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", 256 pcie_ep ? "End Point" : "Root Complex", 257 (uint)pci); 258 if (pci->pme_msg_det) { 259 pci->pme_msg_det = 0xffffffff; 260 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 261 } 262 printf ("\n"); 263 264 /* inbound */ 265 r += fsl_pci_setup_inbound_windows(r); 266 267 /* outbound memory */ 268 pci_set_region(r++, 269 CONFIG_SYS_PCIE2_MEM_BUS, 270 CONFIG_SYS_PCIE2_MEM_PHYS, 271 CONFIG_SYS_PCIE2_MEM_SIZE, 272 PCI_REGION_MEM); 273 274 /* outbound io */ 275 pci_set_region(r++, 276 CONFIG_SYS_PCIE2_IO_BUS, 277 CONFIG_SYS_PCIE2_IO_PHYS, 278 CONFIG_SYS_PCIE2_IO_SIZE, 279 PCI_REGION_IO); 280 281 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 282 /* outbound memory */ 283 pci_set_region(r++, 284 CONFIG_SYS_PCIE2_MEM_BUS2, 285 CONFIG_SYS_PCIE2_MEM_PHYS2, 286 CONFIG_SYS_PCIE2_MEM_SIZE2, 287 PCI_REGION_MEM); 288 #endif 289 hose->region_count = r - hose->regions; 290 hose->first_busno=first_free_busno; 291 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 292 293 fsl_pci_init(hose); 294 first_free_busno=hose->last_busno+1; 295 printf (" PCIE2 on bus %02x - %02x\n", 296 hose->first_busno,hose->last_busno); 297 298 } else { 299 printf (" PCIE2: disabled\n"); 300 } 301 302 } 303 #else 304 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 305 #endif 306 307 308 #ifdef CONFIG_PCI1 309 { 310 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 311 struct pci_controller *hose = &pci1_hose; 312 struct pci_region *r = hose->regions; 313 314 uint pci_agent = (host_agent == 6); 315 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 316 uint pci_32 = 1; 317 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 318 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 319 320 321 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 322 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 323 (pci_32) ? 32 : 64, 324 (pci_speed == 33333000) ? "33" : 325 (pci_speed == 66666000) ? "66" : "unknown", 326 pci_clk_sel ? "sync" : "async", 327 pci_agent ? "agent" : "host", 328 pci_arb ? "arbiter" : "external-arbiter", 329 (uint)pci 330 ); 331 332 /* inbound */ 333 r += fsl_pci_setup_inbound_windows(r); 334 335 /* outbound memory */ 336 pci_set_region(r++, 337 CONFIG_SYS_PCI1_MEM_BUS, 338 CONFIG_SYS_PCI1_MEM_PHYS, 339 CONFIG_SYS_PCI1_MEM_SIZE, 340 PCI_REGION_MEM); 341 342 /* outbound io */ 343 pci_set_region(r++, 344 CONFIG_SYS_PCI1_IO_BUS, 345 CONFIG_SYS_PCI1_IO_PHYS, 346 CONFIG_SYS_PCI1_IO_SIZE, 347 PCI_REGION_IO); 348 349 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2 350 /* outbound memory */ 351 pci_set_region(r++, 352 CONFIG_SYS_PCIE3_MEM_BUS2, 353 CONFIG_SYS_PCIE3_MEM_PHYS2, 354 CONFIG_SYS_PCIE3_MEM_SIZE2, 355 PCI_REGION_MEM); 356 #endif 357 hose->region_count = r - hose->regions; 358 hose->first_busno=first_free_busno; 359 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 360 361 fsl_pci_init(hose); 362 first_free_busno=hose->last_busno+1; 363 printf ("PCI on bus %02x - %02x\n", 364 hose->first_busno,hose->last_busno); 365 } else { 366 printf (" PCI: disabled\n"); 367 } 368 } 369 #else 370 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 371 #endif 372 } 373 374 375 int last_stage_init(void) 376 { 377 return 0; 378 } 379 380 381 unsigned long 382 get_board_sys_clk(ulong dummy) 383 { 384 u8 i, go_bit, rd_clks; 385 ulong val = 0; 386 387 go_bit = in8(PIXIS_BASE + PIXIS_VCTL); 388 go_bit &= 0x01; 389 390 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); 391 rd_clks &= 0x1C; 392 393 /* 394 * Only if both go bit and the SCLK bit in VCFGEN0 are set 395 * should we be using the AUX register. Remember, we also set the 396 * GO bit to boot from the alternate bank on the on-board flash 397 */ 398 399 if (go_bit) { 400 if (rd_clks == 0x1c) 401 i = in8(PIXIS_BASE + PIXIS_AUX); 402 else 403 i = in8(PIXIS_BASE + PIXIS_SPD); 404 } else { 405 i = in8(PIXIS_BASE + PIXIS_SPD); 406 } 407 408 i &= 0x07; 409 410 switch (i) { 411 case 0: 412 val = 33333333; 413 break; 414 case 1: 415 val = 40000000; 416 break; 417 case 2: 418 val = 50000000; 419 break; 420 case 3: 421 val = 66666666; 422 break; 423 case 4: 424 val = 83000000; 425 break; 426 case 5: 427 val = 100000000; 428 break; 429 case 6: 430 val = 133333333; 431 break; 432 case 7: 433 val = 166666666; 434 break; 435 } 436 437 return val; 438 } 439 440 int board_eth_init(bd_t *bis) 441 { 442 #ifdef CONFIG_TSEC_ENET 443 struct tsec_info_struct tsec_info[2]; 444 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 445 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 446 int num = 0; 447 448 #ifdef CONFIG_TSEC1 449 SET_STD_TSEC_INFO(tsec_info[num], 1); 450 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 451 tsec_info[num].flags |= TSEC_SGMII; 452 num++; 453 #endif 454 #ifdef CONFIG_TSEC3 455 SET_STD_TSEC_INFO(tsec_info[num], 3); 456 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 457 tsec_info[num].flags |= TSEC_SGMII; 458 num++; 459 #endif 460 461 if (!num) { 462 printf("No TSECs initialized\n"); 463 464 return 0; 465 } 466 467 if (io_sel & 1) 468 fsl_sgmii_riser_init(tsec_info, num); 469 470 471 tsec_eth_init(bis, tsec_info, num); 472 #endif 473 return pci_eth_init(bis); 474 } 475 476 #if defined(CONFIG_OF_BOARD_SETUP) 477 void ft_board_setup(void *blob, bd_t *bd) 478 { 479 ft_cpu_setup(blob, bd); 480 481 482 #ifdef CONFIG_PCI1 483 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 484 #endif 485 #ifdef CONFIG_PCIE2 486 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 487 #endif 488 #ifdef CONFIG_PCIE1 489 ft_fsl_pci_setup(blob, "pci2", &pcie3_hose); 490 #endif 491 #ifdef CONFIG_PCIE3 492 ft_fsl_pci_setup(blob, "pci3", &pcie2_hose); 493 #endif 494 #ifdef CONFIG_FSL_SGMII_RISER 495 fsl_sgmii_riser_fdt_fixup(blob); 496 #endif 497 } 498 #endif 499