1 /* 2 * Copyright 2007,2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/fsl_pci.h> 30 #include <asm/fsl_ddr_sdram.h> 31 #include <asm/io.h> 32 #include <miiphy.h> 33 #include <libfdt.h> 34 #include <fdt_support.h> 35 #include <tsec.h> 36 #include <netdev.h> 37 38 #include "../common/pixis.h" 39 #include "../common/sgmii_riser.h" 40 41 int checkboard (void) 42 { 43 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 44 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 45 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 46 u8 vboot; 47 u8 *pixis_base = (u8 *)PIXIS_BASE; 48 49 if ((uint)&gur->porpllsr != 0xe00e0000) { 50 printf("immap size error %lx\n",(ulong)&gur->porpllsr); 51 } 52 printf ("Board: MPC8544DS, Sys ID: 0x%02x, " 53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 54 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 55 in_8(pixis_base + PIXIS_PVER)); 56 57 vboot = in_8(pixis_base + PIXIS_VBOOT); 58 if (vboot & PIXIS_VBOOT_FMAP) 59 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); 60 else 61 puts ("Promjet\n"); 62 63 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 64 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 65 ecm->eedr = 0xffffffff; /* Clear ecm errors */ 66 ecm->eeer = 0xffffffff; /* Enable ecm errors */ 67 68 return 0; 69 } 70 71 phys_size_t 72 initdram(int board_type) 73 { 74 long dram_size = 0; 75 76 puts("Initializing\n"); 77 78 dram_size = fsl_ddr_sdram(); 79 80 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 81 82 dram_size *= 0x100000; 83 84 puts(" DDR: "); 85 return dram_size; 86 } 87 88 #ifdef CONFIG_PCI1 89 static struct pci_controller pci1_hose; 90 #endif 91 92 #ifdef CONFIG_PCIE1 93 static struct pci_controller pcie1_hose; 94 #endif 95 96 #ifdef CONFIG_PCIE2 97 static struct pci_controller pcie2_hose; 98 #endif 99 100 #ifdef CONFIG_PCIE3 101 static struct pci_controller pcie3_hose; 102 #endif 103 104 void pci_init_board(void) 105 { 106 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 107 struct fsl_pci_info pci_info[4]; 108 u32 devdisr, pordevsr, io_sel; 109 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 110 int first_free_busno = 0; 111 int num = 0; 112 113 int pcie_ep, pcie_configured; 114 115 devdisr = in_be32(&gur->devdisr); 116 pordevsr = in_be32(&gur->pordevsr); 117 porpllsr = in_be32(&gur->porpllsr); 118 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 119 120 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 121 122 if (io_sel & 1) { 123 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 124 printf (" eTSEC1 is in sgmii mode.\n"); 125 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 126 printf (" eTSEC3 is in sgmii mode.\n"); 127 } 128 puts("\n"); 129 130 #ifdef CONFIG_PCIE3 131 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); 132 133 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 134 SET_STD_PCIE_INFO(pci_info[num], 3); 135 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); 136 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2 137 /* outbound memory */ 138 pci_set_region(&pcie3_hose.regions[0], 139 CONFIG_SYS_PCIE3_MEM_BUS2, 140 CONFIG_SYS_PCIE3_MEM_PHYS2, 141 CONFIG_SYS_PCIE3_MEM_SIZE2, 142 PCI_REGION_MEM); 143 144 pcie3_hose.region_count = 1; 145 #endif 146 printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", 147 pcie_ep ? "Endpoint" : "Root Complex", 148 pci_info[num].regs); 149 first_free_busno = fsl_pci_init_port(&pci_info[num++], 150 &pcie3_hose, first_free_busno); 151 152 /* 153 * Activate ULI1575 legacy chip by performing a fake 154 * memory access. Needed to make ULI RTC work. 155 */ 156 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); 157 } else { 158 printf (" PCIE3: disabled\n"); 159 } 160 puts("\n"); 161 #else 162 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 163 #endif 164 165 #ifdef CONFIG_PCIE1 166 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 167 168 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 169 SET_STD_PCIE_INFO(pci_info[num], 1); 170 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 171 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 172 /* outbound memory */ 173 pci_set_region(&pcie1_hose.regions[0], 174 CONFIG_SYS_PCIE1_MEM_BUS2, 175 CONFIG_SYS_PCIE1_MEM_PHYS2, 176 CONFIG_SYS_PCIE1_MEM_SIZE2, 177 PCI_REGION_MEM); 178 179 pcie1_hose.region_count = 1; 180 #endif 181 printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", 182 pcie_ep ? "Endpoint" : "Root Complex", 183 pci_info[num].regs); 184 185 first_free_busno = fsl_pci_init_port(&pci_info[num++], 186 &pcie1_hose, first_free_busno); 187 } else { 188 printf (" PCIE1: disabled\n"); 189 } 190 191 puts("\n"); 192 #else 193 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 194 #endif 195 196 #ifdef CONFIG_PCIE2 197 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 198 199 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ 200 SET_STD_PCIE_INFO(pci_info[num], 2); 201 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 202 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 203 /* outbound memory */ 204 pci_set_region(&pcie2_hose.regions[0], 205 CONFIG_SYS_PCIE2_MEM_BUS2, 206 CONFIG_SYS_PCIE2_MEM_PHYS2, 207 CONFIG_SYS_PCIE2_MEM_SIZE2, 208 PCI_REGION_MEM); 209 210 pcie2_hose.region_count = 1; 211 #endif 212 printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", 213 pcie_ep ? "Endpoint" : "Root Complex", 214 pci_info[num].regs); 215 first_free_busno = fsl_pci_init_port(&pci_info[num++], 216 &pcie2_hose, first_free_busno); 217 } else { 218 printf (" PCIE2: disabled\n"); 219 } 220 221 puts("\n"); 222 #else 223 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 224 #endif 225 226 #ifdef CONFIG_PCI1 227 pci_speed = 66666000; 228 pci_32 = 1; 229 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 230 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 231 232 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 233 SET_STD_PCI_INFO(pci_info[num], 1); 234 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 235 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 236 (pci_32) ? 32 : 64, 237 (pci_speed == 33333000) ? "33" : 238 (pci_speed == 66666000) ? "66" : "unknown", 239 pci_clk_sel ? "sync" : "async", 240 pci_agent ? "agent" : "host", 241 pci_arb ? "arbiter" : "external-arbiter", 242 pci_info[num].regs); 243 244 first_free_busno = fsl_pci_init_port(&pci_info[num++], 245 &pci1_hose, first_free_busno); 246 } else { 247 printf (" PCI: disabled\n"); 248 } 249 250 puts("\n"); 251 #else 252 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 253 #endif 254 } 255 256 257 int last_stage_init(void) 258 { 259 return 0; 260 } 261 262 263 unsigned long 264 get_board_sys_clk(ulong dummy) 265 { 266 u8 i, go_bit, rd_clks; 267 ulong val = 0; 268 u8 *pixis_base = (u8 *)PIXIS_BASE; 269 270 go_bit = in_8(pixis_base + PIXIS_VCTL); 271 go_bit &= 0x01; 272 273 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); 274 rd_clks &= 0x1C; 275 276 /* 277 * Only if both go bit and the SCLK bit in VCFGEN0 are set 278 * should we be using the AUX register. Remember, we also set the 279 * GO bit to boot from the alternate bank on the on-board flash 280 */ 281 282 if (go_bit) { 283 if (rd_clks == 0x1c) 284 i = in_8(pixis_base + PIXIS_AUX); 285 else 286 i = in_8(pixis_base + PIXIS_SPD); 287 } else { 288 i = in_8(pixis_base + PIXIS_SPD); 289 } 290 291 i &= 0x07; 292 293 switch (i) { 294 case 0: 295 val = 33333333; 296 break; 297 case 1: 298 val = 40000000; 299 break; 300 case 2: 301 val = 50000000; 302 break; 303 case 3: 304 val = 66666666; 305 break; 306 case 4: 307 val = 83000000; 308 break; 309 case 5: 310 val = 100000000; 311 break; 312 case 6: 313 val = 133333333; 314 break; 315 case 7: 316 val = 166666666; 317 break; 318 } 319 320 return val; 321 } 322 323 int board_eth_init(bd_t *bis) 324 { 325 #ifdef CONFIG_TSEC_ENET 326 struct tsec_info_struct tsec_info[2]; 327 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 328 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 329 int num = 0; 330 331 #ifdef CONFIG_TSEC1 332 SET_STD_TSEC_INFO(tsec_info[num], 1); 333 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 334 tsec_info[num].flags |= TSEC_SGMII; 335 num++; 336 #endif 337 #ifdef CONFIG_TSEC3 338 SET_STD_TSEC_INFO(tsec_info[num], 3); 339 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 340 tsec_info[num].flags |= TSEC_SGMII; 341 num++; 342 #endif 343 344 if (!num) { 345 printf("No TSECs initialized\n"); 346 347 return 0; 348 } 349 350 if (io_sel & 1) 351 fsl_sgmii_riser_init(tsec_info, num); 352 353 354 tsec_eth_init(bis, tsec_info, num); 355 #endif 356 return pci_eth_init(bis); 357 } 358 359 #if defined(CONFIG_OF_BOARD_SETUP) 360 void ft_board_setup(void *blob, bd_t *bd) 361 { 362 ft_cpu_setup(blob, bd); 363 364 365 #ifdef CONFIG_PCI1 366 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 367 #endif 368 #ifdef CONFIG_PCIE2 369 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 370 #endif 371 #ifdef CONFIG_PCIE1 372 ft_fsl_pci_setup(blob, "pci2", &pcie3_hose); 373 #endif 374 #ifdef CONFIG_PCIE3 375 ft_fsl_pci_setup(blob, "pci3", &pcie2_hose); 376 #endif 377 #ifdef CONFIG_FSL_SGMII_RISER 378 fsl_sgmii_riser_fdt_fixup(blob); 379 #endif 380 } 381 #endif 382