1 /* 2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <pci.h> 10 #include <asm/processor.h> 11 #include <asm/mmu.h> 12 #include <asm/immap_85xx.h> 13 #include <asm/fsl_pci.h> 14 #include <fsl_ddr_sdram.h> 15 #include <asm/fsl_serdes.h> 16 #include <asm/io.h> 17 #include <miiphy.h> 18 #include <libfdt.h> 19 #include <fdt_support.h> 20 #include <fsl_mdio.h> 21 #include <tsec.h> 22 #include <netdev.h> 23 24 #include "../common/sgmii_riser.h" 25 26 int checkboard (void) 27 { 28 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 29 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 30 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 31 u8 vboot; 32 u8 *pixis_base = (u8 *)PIXIS_BASE; 33 34 if ((uint)&gur->porpllsr != 0xe00e0000) { 35 printf("immap size error %lx\n",(ulong)&gur->porpllsr); 36 } 37 printf ("Board: MPC8544DS, Sys ID: 0x%02x, " 38 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 39 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 40 in_8(pixis_base + PIXIS_PVER)); 41 42 vboot = in_8(pixis_base + PIXIS_VBOOT); 43 if (vboot & PIXIS_VBOOT_FMAP) 44 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); 45 else 46 puts ("Promjet\n"); 47 48 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 49 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 50 ecm->eedr = 0xffffffff; /* Clear ecm errors */ 51 ecm->eeer = 0xffffffff; /* Enable ecm errors */ 52 53 return 0; 54 } 55 56 #ifdef CONFIG_PCI1 57 static struct pci_controller pci1_hose; 58 #endif 59 60 #ifdef CONFIG_PCIE3 61 static struct pci_controller pcie3_hose; 62 #endif 63 64 void pci_init_board(void) 65 { 66 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 67 struct fsl_pci_info pci_info; 68 u32 devdisr, pordevsr, io_sel; 69 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 70 int first_free_busno = 0; 71 72 int pcie_ep, pcie_configured; 73 74 devdisr = in_be32(&gur->devdisr); 75 pordevsr = in_be32(&gur->pordevsr); 76 porpllsr = in_be32(&gur->porpllsr); 77 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 78 79 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 80 81 puts("\n"); 82 83 #ifdef CONFIG_PCIE3 84 pcie_configured = is_serdes_configured(PCIE3); 85 86 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 87 /* contains both PCIE3 MEM & IO space */ 88 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, 89 LAW_TRGT_IF_PCIE_3); 90 SET_STD_PCIE_INFO(pci_info, 3); 91 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs); 92 93 /* outbound memory */ 94 pci_set_region(&pcie3_hose.regions[0], 95 CONFIG_SYS_PCIE3_MEM_BUS2, 96 CONFIG_SYS_PCIE3_MEM_PHYS2, 97 CONFIG_SYS_PCIE3_MEM_SIZE2, 98 PCI_REGION_MEM); 99 100 pcie3_hose.region_count = 1; 101 102 printf("PCIE3: connected to ULI as %s (base addr %lx)\n", 103 pcie_ep ? "Endpoint" : "Root Complex", 104 pci_info.regs); 105 first_free_busno = fsl_pci_init_port(&pci_info, 106 &pcie3_hose, first_free_busno); 107 108 /* 109 * Activate ULI1575 legacy chip by performing a fake 110 * memory access. Needed to make ULI RTC work. 111 */ 112 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); 113 } else { 114 printf("PCIE3: disabled\n"); 115 } 116 puts("\n"); 117 #else 118 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 119 #endif 120 121 #ifdef CONFIG_PCIE1 122 SET_STD_PCIE_INFO(pci_info, 1); 123 first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info); 124 #else 125 setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ 126 #endif 127 128 #ifdef CONFIG_PCIE2 129 SET_STD_PCIE_INFO(pci_info, 2); 130 first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info); 131 #else 132 setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ 133 #endif 134 135 #ifdef CONFIG_PCI1 136 pci_speed = 66666000; 137 pci_32 = 1; 138 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 139 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 140 141 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 142 SET_STD_PCI_INFO(pci_info, 1); 143 set_next_law(pci_info.mem_phys, 144 law_size_bits(pci_info.mem_size), pci_info.law); 145 set_next_law(pci_info.io_phys, 146 law_size_bits(pci_info.io_size), pci_info.law); 147 148 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 149 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 150 (pci_32) ? 32 : 64, 151 (pci_speed == 33333000) ? "33" : 152 (pci_speed == 66666000) ? "66" : "unknown", 153 pci_clk_sel ? "sync" : "async", 154 pci_agent ? "agent" : "host", 155 pci_arb ? "arbiter" : "external-arbiter", 156 pci_info.regs); 157 158 first_free_busno = fsl_pci_init_port(&pci_info, 159 &pci1_hose, first_free_busno); 160 } else { 161 printf("PCI: disabled\n"); 162 } 163 164 puts("\n"); 165 #else 166 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 167 #endif 168 } 169 170 int last_stage_init(void) 171 { 172 return 0; 173 } 174 175 176 unsigned long 177 get_board_sys_clk(ulong dummy) 178 { 179 u8 i, go_bit, rd_clks; 180 ulong val = 0; 181 u8 *pixis_base = (u8 *)PIXIS_BASE; 182 183 go_bit = in_8(pixis_base + PIXIS_VCTL); 184 go_bit &= 0x01; 185 186 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); 187 rd_clks &= 0x1C; 188 189 /* 190 * Only if both go bit and the SCLK bit in VCFGEN0 are set 191 * should we be using the AUX register. Remember, we also set the 192 * GO bit to boot from the alternate bank on the on-board flash 193 */ 194 195 if (go_bit) { 196 if (rd_clks == 0x1c) 197 i = in_8(pixis_base + PIXIS_AUX); 198 else 199 i = in_8(pixis_base + PIXIS_SPD); 200 } else { 201 i = in_8(pixis_base + PIXIS_SPD); 202 } 203 204 i &= 0x07; 205 206 switch (i) { 207 case 0: 208 val = 33333333; 209 break; 210 case 1: 211 val = 40000000; 212 break; 213 case 2: 214 val = 50000000; 215 break; 216 case 3: 217 val = 66666666; 218 break; 219 case 4: 220 val = 83000000; 221 break; 222 case 5: 223 val = 100000000; 224 break; 225 case 6: 226 val = 133333333; 227 break; 228 case 7: 229 val = 166666666; 230 break; 231 } 232 233 return val; 234 } 235 236 237 #define MIIM_CIS8204_SLED_CON 0x1b 238 #define MIIM_CIS8204_SLEDCON_INIT 0x1115 239 /* 240 * Hack to write all 4 PHYs with the LED values 241 */ 242 int board_phy_config(struct phy_device *phydev) 243 { 244 static int do_once; 245 uint phyid; 246 struct mii_dev *bus = phydev->bus; 247 248 if (phydev->drv->config) 249 phydev->drv->config(phydev); 250 if (do_once) 251 return 0; 252 253 for (phyid = 0; phyid < 4; phyid++) 254 bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON, 255 MIIM_CIS8204_SLEDCON_INIT); 256 257 do_once = 1; 258 259 return 0; 260 } 261 262 263 int board_eth_init(bd_t *bis) 264 { 265 #ifdef CONFIG_TSEC_ENET 266 struct fsl_pq_mdio_info mdio_info; 267 struct tsec_info_struct tsec_info[2]; 268 int num = 0; 269 270 #ifdef CONFIG_TSEC1 271 SET_STD_TSEC_INFO(tsec_info[num], 1); 272 if (is_serdes_configured(SGMII_TSEC1)) { 273 puts("eTSEC1 is in sgmii mode.\n"); 274 tsec_info[num].flags |= TSEC_SGMII; 275 } 276 num++; 277 #endif 278 #ifdef CONFIG_TSEC3 279 SET_STD_TSEC_INFO(tsec_info[num], 3); 280 if (is_serdes_configured(SGMII_TSEC3)) { 281 puts("eTSEC3 is in sgmii mode.\n"); 282 tsec_info[num].flags |= TSEC_SGMII; 283 } 284 num++; 285 #endif 286 287 if (!num) { 288 printf("No TSECs initialized\n"); 289 290 return 0; 291 } 292 293 if (is_serdes_configured(SGMII_TSEC1) || 294 is_serdes_configured(SGMII_TSEC3)) { 295 fsl_sgmii_riser_init(tsec_info, num); 296 } 297 298 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 299 mdio_info.name = DEFAULT_MII_NAME; 300 fsl_pq_mdio_init(bis, &mdio_info); 301 302 tsec_eth_init(bis, tsec_info, num); 303 #endif 304 return pci_eth_init(bis); 305 } 306 307 #if defined(CONFIG_OF_BOARD_SETUP) 308 void ft_board_setup(void *blob, bd_t *bd) 309 { 310 ft_cpu_setup(blob, bd); 311 312 FT_FSL_PCI_SETUP; 313 314 #ifdef CONFIG_FSL_SGMII_RISER 315 fsl_sgmii_riser_fdt_fixup(blob); 316 #endif 317 } 318 #endif 319