1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/fsl_pci.h> 30 #include <asm/fsl_ddr_sdram.h> 31 #include <asm/io.h> 32 #include <miiphy.h> 33 #include <libfdt.h> 34 #include <fdt_support.h> 35 #include <tsec.h> 36 #include <netdev.h> 37 38 #include "../common/pixis.h" 39 #include "../common/sgmii_riser.h" 40 41 int checkboard (void) 42 { 43 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 44 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 45 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 46 u8 vboot; 47 u8 *pixis_base = (u8 *)PIXIS_BASE; 48 49 if ((uint)&gur->porpllsr != 0xe00e0000) { 50 printf("immap size error %lx\n",(ulong)&gur->porpllsr); 51 } 52 printf ("Board: MPC8544DS, Sys ID: 0x%02x, " 53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 54 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 55 in_8(pixis_base + PIXIS_PVER)); 56 57 vboot = in_8(pixis_base + PIXIS_VBOOT); 58 if (vboot & PIXIS_VBOOT_FMAP) 59 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); 60 else 61 puts ("Promjet\n"); 62 63 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 64 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 65 ecm->eedr = 0xffffffff; /* Clear ecm errors */ 66 ecm->eeer = 0xffffffff; /* Enable ecm errors */ 67 68 return 0; 69 } 70 71 phys_size_t 72 initdram(int board_type) 73 { 74 long dram_size = 0; 75 76 puts("Initializing\n"); 77 78 dram_size = fsl_ddr_sdram(); 79 80 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 81 82 dram_size *= 0x100000; 83 84 puts(" DDR: "); 85 return dram_size; 86 } 87 88 #ifdef CONFIG_PCI1 89 static struct pci_controller pci1_hose; 90 #endif 91 92 #ifdef CONFIG_PCIE1 93 static struct pci_controller pcie1_hose; 94 #endif 95 96 #ifdef CONFIG_PCIE2 97 static struct pci_controller pcie2_hose; 98 #endif 99 100 #ifdef CONFIG_PCIE3 101 static struct pci_controller pcie3_hose; 102 #endif 103 104 int first_free_busno=0; 105 106 void 107 pci_init_board(void) 108 { 109 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 110 uint devdisr = gur->devdisr; 111 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 112 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 113 114 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 115 devdisr, io_sel, host_agent); 116 117 if (io_sel & 1) { 118 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 119 printf (" eTSEC1 is in sgmii mode.\n"); 120 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 121 printf (" eTSEC3 is in sgmii mode.\n"); 122 } 123 124 #ifdef CONFIG_PCIE3 125 { 126 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 127 struct pci_controller *hose = &pcie3_hose; 128 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); 129 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); 130 struct pci_region *r = hose->regions; 131 132 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 133 printf ("\n PCIE3 connected to ULI as %s (base address %x)", 134 pcie_ep ? "End Point" : "Root Complex", 135 (uint)pci); 136 if (pci->pme_msg_det) { 137 pci->pme_msg_det = 0xffffffff; 138 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 139 } 140 printf ("\n"); 141 142 /* outbound memory */ 143 pci_set_region(r++, 144 CONFIG_SYS_PCIE3_MEM_BUS, 145 CONFIG_SYS_PCIE3_MEM_PHYS, 146 CONFIG_SYS_PCIE3_MEM_SIZE, 147 PCI_REGION_MEM); 148 149 /* outbound io */ 150 pci_set_region(r++, 151 CONFIG_SYS_PCIE3_IO_BUS, 152 CONFIG_SYS_PCIE3_IO_PHYS, 153 CONFIG_SYS_PCIE3_IO_SIZE, 154 PCI_REGION_IO); 155 156 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2 157 /* outbound memory */ 158 pci_set_region(r++, 159 CONFIG_SYS_PCIE3_MEM_BUS2, 160 CONFIG_SYS_PCIE3_MEM_PHYS2, 161 CONFIG_SYS_PCIE3_MEM_SIZE2, 162 PCI_REGION_MEM); 163 #endif 164 hose->region_count = r - hose->regions; 165 hose->first_busno=first_free_busno; 166 167 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 168 169 first_free_busno=hose->last_busno+1; 170 printf (" PCIE3 on bus %02x - %02x\n", 171 hose->first_busno,hose->last_busno); 172 173 /* 174 * Activate ULI1575 legacy chip by performing a fake 175 * memory access. Needed to make ULI RTC work. 176 */ 177 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); 178 } else { 179 printf (" PCIE3: disabled\n"); 180 } 181 182 } 183 #else 184 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 185 #endif 186 187 #ifdef CONFIG_PCIE1 188 { 189 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 190 struct pci_controller *hose = &pcie1_hose; 191 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); 192 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 193 struct pci_region *r = hose->regions; 194 195 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 196 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", 197 pcie_ep ? "End Point" : "Root Complex", 198 (uint)pci); 199 if (pci->pme_msg_det) { 200 pci->pme_msg_det = 0xffffffff; 201 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 202 } 203 printf ("\n"); 204 205 /* outbound memory */ 206 pci_set_region(r++, 207 CONFIG_SYS_PCIE1_MEM_BUS, 208 CONFIG_SYS_PCIE1_MEM_PHYS, 209 CONFIG_SYS_PCIE1_MEM_SIZE, 210 PCI_REGION_MEM); 211 212 /* outbound io */ 213 pci_set_region(r++, 214 CONFIG_SYS_PCIE1_IO_BUS, 215 CONFIG_SYS_PCIE1_IO_PHYS, 216 CONFIG_SYS_PCIE1_IO_SIZE, 217 PCI_REGION_IO); 218 219 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 220 /* outbound memory */ 221 pci_set_region(r++, 222 CONFIG_SYS_PCIE1_MEM_BUS2, 223 CONFIG_SYS_PCIE1_MEM_PHYS2, 224 CONFIG_SYS_PCIE1_MEM_SIZE2, 225 PCI_REGION_MEM); 226 #endif 227 hose->region_count = r - hose->regions; 228 hose->first_busno=first_free_busno; 229 230 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 231 232 first_free_busno=hose->last_busno+1; 233 printf(" PCIE1 on bus %02x - %02x\n", 234 hose->first_busno,hose->last_busno); 235 236 } else { 237 printf (" PCIE1: disabled\n"); 238 } 239 240 } 241 #else 242 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 243 #endif 244 245 #ifdef CONFIG_PCIE2 246 { 247 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 248 struct pci_controller *hose = &pcie2_hose; 249 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); 250 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 251 struct pci_region *r = hose->regions; 252 253 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 254 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", 255 pcie_ep ? "End Point" : "Root Complex", 256 (uint)pci); 257 if (pci->pme_msg_det) { 258 pci->pme_msg_det = 0xffffffff; 259 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 260 } 261 printf ("\n"); 262 263 /* outbound memory */ 264 pci_set_region(r++, 265 CONFIG_SYS_PCIE2_MEM_BUS, 266 CONFIG_SYS_PCIE2_MEM_PHYS, 267 CONFIG_SYS_PCIE2_MEM_SIZE, 268 PCI_REGION_MEM); 269 270 /* outbound io */ 271 pci_set_region(r++, 272 CONFIG_SYS_PCIE2_IO_BUS, 273 CONFIG_SYS_PCIE2_IO_PHYS, 274 CONFIG_SYS_PCIE2_IO_SIZE, 275 PCI_REGION_IO); 276 277 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 278 /* outbound memory */ 279 pci_set_region(r++, 280 CONFIG_SYS_PCIE2_MEM_BUS2, 281 CONFIG_SYS_PCIE2_MEM_PHYS2, 282 CONFIG_SYS_PCIE2_MEM_SIZE2, 283 PCI_REGION_MEM); 284 #endif 285 hose->region_count = r - hose->regions; 286 hose->first_busno=first_free_busno; 287 288 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 289 first_free_busno=hose->last_busno+1; 290 printf (" PCIE2 on bus %02x - %02x\n", 291 hose->first_busno,hose->last_busno); 292 293 } else { 294 printf (" PCIE2: disabled\n"); 295 } 296 297 } 298 #else 299 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 300 #endif 301 302 303 #ifdef CONFIG_PCI1 304 { 305 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 306 struct pci_controller *hose = &pci1_hose; 307 struct pci_region *r = hose->regions; 308 309 uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent); 310 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 311 uint pci_32 = 1; 312 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 313 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 314 315 316 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 317 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 318 (pci_32) ? 32 : 64, 319 (pci_speed == 33333000) ? "33" : 320 (pci_speed == 66666000) ? "66" : "unknown", 321 pci_clk_sel ? "sync" : "async", 322 pci_agent ? "agent" : "host", 323 pci_arb ? "arbiter" : "external-arbiter", 324 (uint)pci 325 ); 326 327 /* outbound memory */ 328 pci_set_region(r++, 329 CONFIG_SYS_PCI1_MEM_BUS, 330 CONFIG_SYS_PCI1_MEM_PHYS, 331 CONFIG_SYS_PCI1_MEM_SIZE, 332 PCI_REGION_MEM); 333 334 /* outbound io */ 335 pci_set_region(r++, 336 CONFIG_SYS_PCI1_IO_BUS, 337 CONFIG_SYS_PCI1_IO_PHYS, 338 CONFIG_SYS_PCI1_IO_SIZE, 339 PCI_REGION_IO); 340 341 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2 342 /* outbound memory */ 343 pci_set_region(r++, 344 CONFIG_SYS_PCIE3_MEM_BUS2, 345 CONFIG_SYS_PCIE3_MEM_PHYS2, 346 CONFIG_SYS_PCIE3_MEM_SIZE2, 347 PCI_REGION_MEM); 348 #endif 349 hose->region_count = r - hose->regions; 350 hose->first_busno=first_free_busno; 351 352 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 353 first_free_busno=hose->last_busno+1; 354 printf ("PCI on bus %02x - %02x\n", 355 hose->first_busno,hose->last_busno); 356 } else { 357 printf (" PCI: disabled\n"); 358 } 359 } 360 #else 361 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 362 #endif 363 } 364 365 366 int last_stage_init(void) 367 { 368 return 0; 369 } 370 371 372 unsigned long 373 get_board_sys_clk(ulong dummy) 374 { 375 u8 i, go_bit, rd_clks; 376 ulong val = 0; 377 u8 *pixis_base = (u8 *)PIXIS_BASE; 378 379 go_bit = in_8(pixis_base + PIXIS_VCTL); 380 go_bit &= 0x01; 381 382 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); 383 rd_clks &= 0x1C; 384 385 /* 386 * Only if both go bit and the SCLK bit in VCFGEN0 are set 387 * should we be using the AUX register. Remember, we also set the 388 * GO bit to boot from the alternate bank on the on-board flash 389 */ 390 391 if (go_bit) { 392 if (rd_clks == 0x1c) 393 i = in_8(pixis_base + PIXIS_AUX); 394 else 395 i = in_8(pixis_base + PIXIS_SPD); 396 } else { 397 i = in_8(pixis_base + PIXIS_SPD); 398 } 399 400 i &= 0x07; 401 402 switch (i) { 403 case 0: 404 val = 33333333; 405 break; 406 case 1: 407 val = 40000000; 408 break; 409 case 2: 410 val = 50000000; 411 break; 412 case 3: 413 val = 66666666; 414 break; 415 case 4: 416 val = 83000000; 417 break; 418 case 5: 419 val = 100000000; 420 break; 421 case 6: 422 val = 133333333; 423 break; 424 case 7: 425 val = 166666666; 426 break; 427 } 428 429 return val; 430 } 431 432 int board_eth_init(bd_t *bis) 433 { 434 #ifdef CONFIG_TSEC_ENET 435 struct tsec_info_struct tsec_info[2]; 436 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 437 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 438 int num = 0; 439 440 #ifdef CONFIG_TSEC1 441 SET_STD_TSEC_INFO(tsec_info[num], 1); 442 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 443 tsec_info[num].flags |= TSEC_SGMII; 444 num++; 445 #endif 446 #ifdef CONFIG_TSEC3 447 SET_STD_TSEC_INFO(tsec_info[num], 3); 448 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 449 tsec_info[num].flags |= TSEC_SGMII; 450 num++; 451 #endif 452 453 if (!num) { 454 printf("No TSECs initialized\n"); 455 456 return 0; 457 } 458 459 if (io_sel & 1) 460 fsl_sgmii_riser_init(tsec_info, num); 461 462 463 tsec_eth_init(bis, tsec_info, num); 464 #endif 465 return pci_eth_init(bis); 466 } 467 468 #if defined(CONFIG_OF_BOARD_SETUP) 469 void ft_board_setup(void *blob, bd_t *bd) 470 { 471 ft_cpu_setup(blob, bd); 472 473 474 #ifdef CONFIG_PCI1 475 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 476 #endif 477 #ifdef CONFIG_PCIE2 478 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 479 #endif 480 #ifdef CONFIG_PCIE1 481 ft_fsl_pci_setup(blob, "pci2", &pcie3_hose); 482 #endif 483 #ifdef CONFIG_PCIE3 484 ft_fsl_pci_setup(blob, "pci3", &pcie2_hose); 485 #endif 486 #ifdef CONFIG_FSL_SGMII_RISER 487 fsl_sgmii_riser_fdt_fixup(blob); 488 #endif 489 } 490 #endif 491