1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <command.h>
8 #include <pci.h>
9 #include <asm/processor.h>
10 #include <asm/mmu.h>
11 #include <asm/immap_85xx.h>
12 #include <asm/fsl_pci.h>
13 #include <fsl_ddr_sdram.h>
14 #include <asm/fsl_serdes.h>
15 #include <asm/io.h>
16 #include <miiphy.h>
17 #include <linux/libfdt.h>
18 #include <fdt_support.h>
19 #include <fsl_mdio.h>
20 #include <tsec.h>
21 #include <netdev.h>
22 
23 #include "../common/sgmii_riser.h"
24 
25 int checkboard (void)
26 {
27 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
28 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
29 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
30 	u8 vboot;
31 	u8 *pixis_base = (u8 *)PIXIS_BASE;
32 
33 	if ((uint)&gur->porpllsr != 0xe00e0000) {
34 		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
35 	}
36 	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
37 		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
38 		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
39 		in_8(pixis_base + PIXIS_PVER));
40 
41 	vboot = in_8(pixis_base + PIXIS_VBOOT);
42 	if (vboot & PIXIS_VBOOT_FMAP)
43 		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
44 	else
45 		puts ("Promjet\n");
46 
47 	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
48 	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
49 	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
50 	ecm->eeer = 0xffffffff;		/* Enable ecm errors */
51 
52 	return 0;
53 }
54 
55 #ifdef CONFIG_PCI1
56 static struct pci_controller pci1_hose;
57 #endif
58 
59 #ifdef CONFIG_PCIE3
60 static struct pci_controller pcie3_hose;
61 #endif
62 
63 void pci_init_board(void)
64 {
65 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
66 	struct fsl_pci_info pci_info;
67 	u32 devdisr, pordevsr, io_sel;
68 	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
69 	int first_free_busno = 0;
70 
71 	int pcie_ep, pcie_configured;
72 
73 	devdisr = in_be32(&gur->devdisr);
74 	pordevsr = in_be32(&gur->pordevsr);
75 	porpllsr = in_be32(&gur->porpllsr);
76 	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
77 
78 	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
79 
80 	puts("\n");
81 
82 #ifdef CONFIG_PCIE3
83 	pcie_configured = is_serdes_configured(PCIE3);
84 
85 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
86 		/* contains both PCIE3 MEM & IO space */
87 		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
88 				LAW_TRGT_IF_PCIE_3);
89 		SET_STD_PCIE_INFO(pci_info, 3);
90 		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
91 
92 		/* outbound memory */
93 		pci_set_region(&pcie3_hose.regions[0],
94 			       CONFIG_SYS_PCIE3_MEM_BUS2,
95 			       CONFIG_SYS_PCIE3_MEM_PHYS2,
96 			       CONFIG_SYS_PCIE3_MEM_SIZE2,
97 			       PCI_REGION_MEM);
98 
99 		pcie3_hose.region_count = 1;
100 
101 		printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
102 			pcie_ep ? "Endpoint" : "Root Complex",
103 			pci_info.regs);
104 		first_free_busno = fsl_pci_init_port(&pci_info,
105 					&pcie3_hose, first_free_busno);
106 
107 		/*
108 		 * Activate ULI1575 legacy chip by performing a fake
109 		 * memory access.  Needed to make ULI RTC work.
110 		 */
111 		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
112 	} else {
113 		printf("PCIE3: disabled\n");
114 	}
115 	puts("\n");
116 #else
117 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
118 #endif
119 
120 #ifdef CONFIG_PCIE1
121 	SET_STD_PCIE_INFO(pci_info, 1);
122 	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
123 #else
124 	setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
125 #endif
126 
127 #ifdef CONFIG_PCIE2
128 	SET_STD_PCIE_INFO(pci_info, 2);
129 	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
130 #else
131 	setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
132 #endif
133 
134 #ifdef CONFIG_PCI1
135 	pci_speed = 66666000;
136 	pci_32 = 1;
137 	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
138 	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
139 
140 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
141 		SET_STD_PCI_INFO(pci_info, 1);
142 		set_next_law(pci_info.mem_phys,
143 			law_size_bits(pci_info.mem_size), pci_info.law);
144 		set_next_law(pci_info.io_phys,
145 			law_size_bits(pci_info.io_size), pci_info.law);
146 
147 		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
148 		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
149 			(pci_32) ? 32 : 64,
150 			(pci_speed == 33333000) ? "33" :
151 			(pci_speed == 66666000) ? "66" : "unknown",
152 			pci_clk_sel ? "sync" : "async",
153 			pci_agent ? "agent" : "host",
154 			pci_arb ? "arbiter" : "external-arbiter",
155 			pci_info.regs);
156 
157 		first_free_busno = fsl_pci_init_port(&pci_info,
158 					&pci1_hose, first_free_busno);
159 	} else {
160 		printf("PCI: disabled\n");
161 	}
162 
163 	puts("\n");
164 #else
165 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
166 #endif
167 }
168 
169 int last_stage_init(void)
170 {
171 	return 0;
172 }
173 
174 
175 unsigned long
176 get_board_sys_clk(ulong dummy)
177 {
178 	u8 i, go_bit, rd_clks;
179 	ulong val = 0;
180 	u8 *pixis_base = (u8 *)PIXIS_BASE;
181 
182 	go_bit = in_8(pixis_base + PIXIS_VCTL);
183 	go_bit &= 0x01;
184 
185 	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
186 	rd_clks &= 0x1C;
187 
188 	/*
189 	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
190 	 * should we be using the AUX register. Remember, we also set the
191 	 * GO bit to boot from the alternate bank on the on-board flash
192 	 */
193 
194 	if (go_bit) {
195 		if (rd_clks == 0x1c)
196 			i = in_8(pixis_base + PIXIS_AUX);
197 		else
198 			i = in_8(pixis_base + PIXIS_SPD);
199 	} else {
200 		i = in_8(pixis_base + PIXIS_SPD);
201 	}
202 
203 	i &= 0x07;
204 
205 	switch (i) {
206 	case 0:
207 		val = 33333333;
208 		break;
209 	case 1:
210 		val = 40000000;
211 		break;
212 	case 2:
213 		val = 50000000;
214 		break;
215 	case 3:
216 		val = 66666666;
217 		break;
218 	case 4:
219 		val = 83000000;
220 		break;
221 	case 5:
222 		val = 100000000;
223 		break;
224 	case 6:
225 		val = 133333333;
226 		break;
227 	case 7:
228 		val = 166666666;
229 		break;
230 	}
231 
232 	return val;
233 }
234 
235 
236 #define MIIM_CIS8204_SLED_CON		0x1b
237 #define MIIM_CIS8204_SLEDCON_INIT	0x1115
238 /*
239  * Hack to write all 4 PHYs with the LED values
240  */
241 int board_phy_config(struct phy_device *phydev)
242 {
243 	static int do_once;
244 	uint phyid;
245 	struct mii_dev *bus = phydev->bus;
246 
247 	if (phydev->drv->config)
248 		phydev->drv->config(phydev);
249 	if (do_once)
250 		return 0;
251 
252 	for (phyid = 0; phyid < 4; phyid++)
253 		bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
254 				MIIM_CIS8204_SLEDCON_INIT);
255 
256 	do_once = 1;
257 
258 	return 0;
259 }
260 
261 
262 int board_eth_init(bd_t *bis)
263 {
264 #ifdef CONFIG_TSEC_ENET
265 	struct fsl_pq_mdio_info mdio_info;
266 	struct tsec_info_struct tsec_info[2];
267 	int num = 0;
268 
269 #ifdef CONFIG_TSEC1
270 	SET_STD_TSEC_INFO(tsec_info[num], 1);
271 	if (is_serdes_configured(SGMII_TSEC1)) {
272 		puts("eTSEC1 is in sgmii mode.\n");
273 		tsec_info[num].flags |= TSEC_SGMII;
274 	}
275 	num++;
276 #endif
277 #ifdef CONFIG_TSEC3
278 	SET_STD_TSEC_INFO(tsec_info[num], 3);
279 	if (is_serdes_configured(SGMII_TSEC3)) {
280 		puts("eTSEC3 is in sgmii mode.\n");
281 		tsec_info[num].flags |= TSEC_SGMII;
282 	}
283 	num++;
284 #endif
285 
286 	if (!num) {
287 		printf("No TSECs initialized\n");
288 
289 		return 0;
290 	}
291 
292 	if (is_serdes_configured(SGMII_TSEC1) ||
293 	    is_serdes_configured(SGMII_TSEC3)) {
294 		fsl_sgmii_riser_init(tsec_info, num);
295 	}
296 
297 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
298 	mdio_info.name = DEFAULT_MII_NAME;
299 	fsl_pq_mdio_init(bis, &mdio_info);
300 
301 	tsec_eth_init(bis, tsec_info, num);
302 #endif
303 	return pci_eth_init(bis);
304 }
305 
306 #if defined(CONFIG_OF_BOARD_SETUP)
307 int ft_board_setup(void *blob, bd_t *bd)
308 {
309 	ft_cpu_setup(blob, bd);
310 
311 	FT_FSL_PCI_SETUP;
312 
313 #ifdef CONFIG_FSL_SGMII_RISER
314 	fsl_sgmii_riser_fdt_fixup(blob);
315 #endif
316 
317 	return 0;
318 }
319 #endif
320