1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_85xx.h> 28 #include <asm/immap_fsl_pci.h> 29 #include <asm/io.h> 30 #include <spd_sdram.h> 31 #include <miiphy.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 35 #include "../common/pixis.h" 36 37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 38 extern void ddr_enable_ecc(unsigned int dram_size); 39 #endif 40 41 void sdram_init(void); 42 43 int board_early_init_f (void) 44 { 45 return 0; 46 } 47 48 int checkboard (void) 49 { 50 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 51 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 52 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); 53 54 if ((uint)&gur->porpllsr != 0xe00e0000) { 55 printf("immap size error %x\n",&gur->porpllsr); 56 } 57 printf ("Board: MPC8544DS\n"); 58 59 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 60 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 61 ecm->eedr = 0xffffffff; /* Clear ecm errors */ 62 ecm->eeer = 0xffffffff; /* Enable ecm errors */ 63 64 return 0; 65 } 66 67 long int 68 initdram(int board_type) 69 { 70 long dram_size = 0; 71 72 puts("Initializing\n"); 73 74 dram_size = spd_sdram(); 75 76 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 77 /* 78 * Initialize and enable DDR ECC. 79 */ 80 ddr_enable_ecc(dram_size); 81 #endif 82 puts(" DDR: "); 83 return dram_size; 84 } 85 86 #if defined(CFG_DRAM_TEST) 87 int 88 testdram(void) 89 { 90 uint *pstart = (uint *) CFG_MEMTEST_START; 91 uint *pend = (uint *) CFG_MEMTEST_END; 92 uint *p; 93 94 printf("Testing DRAM from 0x%08x to 0x%08x\n", 95 CFG_MEMTEST_START, 96 CFG_MEMTEST_END); 97 98 printf("DRAM test phase 1:\n"); 99 for (p = pstart; p < pend; p++) 100 *p = 0xaaaaaaaa; 101 102 for (p = pstart; p < pend; p++) { 103 if (*p != 0xaaaaaaaa) { 104 printf ("DRAM test fails at: %08x\n", (uint) p); 105 return 1; 106 } 107 } 108 109 printf("DRAM test phase 2:\n"); 110 for (p = pstart; p < pend; p++) 111 *p = 0x55555555; 112 113 for (p = pstart; p < pend; p++) { 114 if (*p != 0x55555555) { 115 printf ("DRAM test fails at: %08x\n", (uint) p); 116 return 1; 117 } 118 } 119 120 printf("DRAM test passed.\n"); 121 return 0; 122 } 123 #endif 124 125 #ifdef CONFIG_PCI1 126 static struct pci_controller pci1_hose; 127 #endif 128 129 #ifdef CONFIG_PCIE1 130 static struct pci_controller pcie1_hose; 131 #endif 132 133 #ifdef CONFIG_PCIE2 134 static struct pci_controller pcie2_hose; 135 #endif 136 137 #ifdef CONFIG_PCIE3 138 static struct pci_controller pcie3_hose; 139 #endif 140 141 int first_free_busno=0; 142 143 void 144 pci_init_board(void) 145 { 146 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 147 uint devdisr = gur->devdisr; 148 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 149 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 150 151 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 152 devdisr, io_sel, host_agent); 153 154 if (io_sel & 1) { 155 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 156 printf (" eTSEC1 is in sgmii mode.\n"); 157 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 158 printf (" eTSEC3 is in sgmii mode.\n"); 159 } 160 161 #ifdef CONFIG_PCIE3 162 { 163 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; 164 extern void fsl_pci_init(struct pci_controller *hose); 165 struct pci_controller *hose = &pcie3_hose; 166 int pcie_ep = (host_agent == 1); 167 int pcie_configured = io_sel >= 1; 168 169 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 170 printf ("\n PCIE3 connected to ULI as %s (base address %x)", 171 pcie_ep ? "End Point" : "Root Complex", 172 (uint)pci); 173 if (pci->pme_msg_det) { 174 pci->pme_msg_det = 0xffffffff; 175 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 176 } 177 printf ("\n"); 178 179 /* inbound */ 180 pci_set_region(hose->regions + 0, 181 CFG_PCI_MEMORY_BUS, 182 CFG_PCI_MEMORY_PHYS, 183 CFG_PCI_MEMORY_SIZE, 184 PCI_REGION_MEM | PCI_REGION_MEMORY); 185 186 /* outbound memory */ 187 pci_set_region(hose->regions + 1, 188 CFG_PCIE3_MEM_BASE, 189 CFG_PCIE3_MEM_PHYS, 190 CFG_PCIE3_MEM_SIZE, 191 PCI_REGION_MEM); 192 193 /* outbound io */ 194 pci_set_region(hose->regions + 2, 195 CFG_PCIE3_IO_BASE, 196 CFG_PCIE3_IO_PHYS, 197 CFG_PCIE3_IO_SIZE, 198 PCI_REGION_IO); 199 200 hose->region_count = 3; 201 #ifdef CFG_PCIE3_MEM_BASE2 202 /* outbound memory */ 203 pci_set_region(hose->regions + 3, 204 CFG_PCIE3_MEM_BASE2, 205 CFG_PCIE3_MEM_PHYS2, 206 CFG_PCIE3_MEM_SIZE2, 207 PCI_REGION_MEM); 208 hose->region_count++; 209 #endif 210 hose->first_busno=first_free_busno; 211 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 212 213 fsl_pci_init(hose); 214 215 first_free_busno=hose->last_busno+1; 216 printf (" PCIE3 on bus %02x - %02x\n", 217 hose->first_busno,hose->last_busno); 218 219 /* 220 * Activate ULI1575 legacy chip by performing a fake 221 * memory access. Needed to make ULI RTC work. 222 */ 223 in_be32((u32 *)CFG_PCIE3_MEM_BASE); 224 } else { 225 printf (" PCIE3: disabled\n"); 226 } 227 228 } 229 #else 230 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 231 #endif 232 233 #ifdef CONFIG_PCIE1 234 { 235 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 236 extern void fsl_pci_init(struct pci_controller *hose); 237 struct pci_controller *hose = &pcie1_hose; 238 int pcie_ep = (host_agent == 5); 239 int pcie_configured = io_sel & 6; 240 241 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 242 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", 243 pcie_ep ? "End Point" : "Root Complex", 244 (uint)pci); 245 if (pci->pme_msg_det) { 246 pci->pme_msg_det = 0xffffffff; 247 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 248 } 249 printf ("\n"); 250 251 /* inbound */ 252 pci_set_region(hose->regions + 0, 253 CFG_PCI_MEMORY_BUS, 254 CFG_PCI_MEMORY_PHYS, 255 CFG_PCI_MEMORY_SIZE, 256 PCI_REGION_MEM | PCI_REGION_MEMORY); 257 258 /* outbound memory */ 259 pci_set_region(hose->regions + 1, 260 CFG_PCIE1_MEM_BASE, 261 CFG_PCIE1_MEM_PHYS, 262 CFG_PCIE1_MEM_SIZE, 263 PCI_REGION_MEM); 264 265 /* outbound io */ 266 pci_set_region(hose->regions + 2, 267 CFG_PCIE1_IO_BASE, 268 CFG_PCIE1_IO_PHYS, 269 CFG_PCIE1_IO_SIZE, 270 PCI_REGION_IO); 271 272 hose->region_count = 3; 273 #ifdef CFG_PCIE1_MEM_BASE2 274 /* outbound memory */ 275 pci_set_region(hose->regions + 3, 276 CFG_PCIE1_MEM_BASE2, 277 CFG_PCIE1_MEM_PHYS2, 278 CFG_PCIE1_MEM_SIZE2, 279 PCI_REGION_MEM); 280 hose->region_count++; 281 #endif 282 hose->first_busno=first_free_busno; 283 284 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 285 286 fsl_pci_init(hose); 287 288 first_free_busno=hose->last_busno+1; 289 printf(" PCIE1 on bus %02x - %02x\n", 290 hose->first_busno,hose->last_busno); 291 292 } else { 293 printf (" PCIE1: disabled\n"); 294 } 295 296 } 297 #else 298 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 299 #endif 300 301 #ifdef CONFIG_PCIE2 302 { 303 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; 304 extern void fsl_pci_init(struct pci_controller *hose); 305 struct pci_controller *hose = &pcie2_hose; 306 int pcie_ep = (host_agent == 3); 307 int pcie_configured = io_sel & 4; 308 309 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 310 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", 311 pcie_ep ? "End Point" : "Root Complex", 312 (uint)pci); 313 if (pci->pme_msg_det) { 314 pci->pme_msg_det = 0xffffffff; 315 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 316 } 317 printf ("\n"); 318 319 /* inbound */ 320 pci_set_region(hose->regions + 0, 321 CFG_PCI_MEMORY_BUS, 322 CFG_PCI_MEMORY_PHYS, 323 CFG_PCI_MEMORY_SIZE, 324 PCI_REGION_MEM | PCI_REGION_MEMORY); 325 326 /* outbound memory */ 327 pci_set_region(hose->regions + 1, 328 CFG_PCIE2_MEM_BASE, 329 CFG_PCIE2_MEM_PHYS, 330 CFG_PCIE2_MEM_SIZE, 331 PCI_REGION_MEM); 332 333 /* outbound io */ 334 pci_set_region(hose->regions + 2, 335 CFG_PCIE2_IO_BASE, 336 CFG_PCIE2_IO_PHYS, 337 CFG_PCIE2_IO_SIZE, 338 PCI_REGION_IO); 339 340 hose->region_count = 3; 341 #ifdef CFG_PCIE2_MEM_BASE2 342 /* outbound memory */ 343 pci_set_region(hose->regions + 3, 344 CFG_PCIE2_MEM_BASE2, 345 CFG_PCIE2_MEM_PHYS2, 346 CFG_PCIE2_MEM_SIZE2, 347 PCI_REGION_MEM); 348 hose->region_count++; 349 #endif 350 hose->first_busno=first_free_busno; 351 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 352 353 fsl_pci_init(hose); 354 first_free_busno=hose->last_busno+1; 355 printf (" PCIE2 on bus %02x - %02x\n", 356 hose->first_busno,hose->last_busno); 357 358 } else { 359 printf (" PCIE2: disabled\n"); 360 } 361 362 } 363 #else 364 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 365 #endif 366 367 368 #ifdef CONFIG_PCI1 369 { 370 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 371 extern void fsl_pci_init(struct pci_controller *hose); 372 struct pci_controller *hose = &pci1_hose; 373 374 uint pci_agent = (host_agent == 6); 375 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 376 uint pci_32 = 1; 377 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 378 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 379 380 381 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 382 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 383 (pci_32) ? 32 : 64, 384 (pci_speed == 33333000) ? "33" : 385 (pci_speed == 66666000) ? "66" : "unknown", 386 pci_clk_sel ? "sync" : "async", 387 pci_agent ? "agent" : "host", 388 pci_arb ? "arbiter" : "external-arbiter", 389 (uint)pci 390 ); 391 392 /* inbound */ 393 pci_set_region(hose->regions + 0, 394 CFG_PCI_MEMORY_BUS, 395 CFG_PCI_MEMORY_PHYS, 396 CFG_PCI_MEMORY_SIZE, 397 PCI_REGION_MEM | PCI_REGION_MEMORY); 398 399 /* outbound memory */ 400 pci_set_region(hose->regions + 1, 401 CFG_PCI1_MEM_BASE, 402 CFG_PCI1_MEM_PHYS, 403 CFG_PCI1_MEM_SIZE, 404 PCI_REGION_MEM); 405 406 /* outbound io */ 407 pci_set_region(hose->regions + 2, 408 CFG_PCI1_IO_BASE, 409 CFG_PCI1_IO_PHYS, 410 CFG_PCI1_IO_SIZE, 411 PCI_REGION_IO); 412 hose->region_count = 3; 413 #ifdef CFG_PCIE3_MEM_BASE2 414 /* outbound memory */ 415 pci_set_region(hose->regions + 3, 416 CFG_PCIE3_MEM_BASE2, 417 CFG_PCIE3_MEM_PHYS2, 418 CFG_PCIE3_MEM_SIZE2, 419 PCI_REGION_MEM); 420 hose->region_count++; 421 #endif 422 hose->first_busno=first_free_busno; 423 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 424 425 fsl_pci_init(hose); 426 first_free_busno=hose->last_busno+1; 427 printf ("PCI on bus %02x - %02x\n", 428 hose->first_busno,hose->last_busno); 429 } else { 430 printf (" PCI: disabled\n"); 431 } 432 } 433 #else 434 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 435 #endif 436 } 437 438 439 int last_stage_init(void) 440 { 441 return 0; 442 } 443 444 445 unsigned long 446 get_board_sys_clk(ulong dummy) 447 { 448 u8 i, go_bit, rd_clks; 449 ulong val = 0; 450 451 go_bit = in8(PIXIS_BASE + PIXIS_VCTL); 452 go_bit &= 0x01; 453 454 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); 455 rd_clks &= 0x1C; 456 457 /* 458 * Only if both go bit and the SCLK bit in VCFGEN0 are set 459 * should we be using the AUX register. Remember, we also set the 460 * GO bit to boot from the alternate bank on the on-board flash 461 */ 462 463 if (go_bit) { 464 if (rd_clks == 0x1c) 465 i = in8(PIXIS_BASE + PIXIS_AUX); 466 else 467 i = in8(PIXIS_BASE + PIXIS_SPD); 468 } else { 469 i = in8(PIXIS_BASE + PIXIS_SPD); 470 } 471 472 i &= 0x07; 473 474 switch (i) { 475 case 0: 476 val = 33333333; 477 break; 478 case 1: 479 val = 40000000; 480 break; 481 case 2: 482 val = 50000000; 483 break; 484 case 3: 485 val = 66666666; 486 break; 487 case 4: 488 val = 83000000; 489 break; 490 case 5: 491 val = 100000000; 492 break; 493 case 6: 494 val = 133333333; 495 break; 496 case 7: 497 val = 166666666; 498 break; 499 } 500 501 return val; 502 } 503 504 #if defined(CONFIG_OF_BOARD_SETUP) 505 506 void 507 ft_board_setup(void *blob, bd_t *bd) 508 { 509 int node, tmp[2]; 510 const char *path; 511 512 ft_cpu_setup(blob, bd); 513 514 node = fdt_path_offset(blob, "/aliases"); 515 tmp[0] = 0; 516 if (node >= 0) { 517 #ifdef CONFIG_PCI1 518 path = fdt_getprop(blob, node, "pci0", NULL); 519 if (path) { 520 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 521 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 522 } 523 #endif 524 #ifdef CONFIG_PCIE2 525 path = fdt_getprop(blob, node, "pci1", NULL); 526 if (path) { 527 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; 528 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 529 } 530 #endif 531 #ifdef CONFIG_PCIE1 532 path = fdt_getprop(blob, node, "pci2", NULL); 533 if (path) { 534 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 535 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 536 } 537 #endif 538 #ifdef CONFIG_PCIE3 539 path = fdt_getprop(blob, node, "pci3", NULL); 540 if (path) { 541 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; 542 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 543 } 544 #endif 545 } 546 } 547 #endif 548